JP6115060B2 - 電子デバイスの製造方法 - Google Patents
電子デバイスの製造方法 Download PDFInfo
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- JP6115060B2 JP6115060B2 JP2012208833A JP2012208833A JP6115060B2 JP 6115060 B2 JP6115060 B2 JP 6115060B2 JP 2012208833 A JP2012208833 A JP 2012208833A JP 2012208833 A JP2012208833 A JP 2012208833A JP 6115060 B2 JP6115060 B2 JP 6115060B2
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Description
本実施形態では、電子デバイスとして、半導体チップをフェイスダウンによりパッケージ基板にフリップチップ接合してなる半導体デバイスを例示する。
半導体チップ10は、Si等の半導体基板11と、素子層12と、保護層13とを備えている。
素子層12は、半導体基板11の表面に、CMOSトランジスタや半導体メモリ等が形成され、これらを覆う層間絶縁膜及び配線等を有するものである。保護層13は、素子層12の表面を保護する絶縁膜である。素子層2の複数の電極パッド12aには、フリップチップ接合のためのハンダバンプ14が設けられる。
パッケージ基板20は、ポリイミド等の基板21と、配線構造22とを備えている。
配線構造22は、基板21の表面に形成されており、図示の例ではライン&スペースの配線22aと、配線22a間の所定部位にハンダバンプ14が接続される接続電極22bとを有している。
従来のパッケージ基板101では、配線構造102の配線102aを覆うようにソルダーレジスト103を形成する必要がある。パッケージ基板20は、このソルダーレジストが不要であり、これを有しない構成とされる。また、従来のパッケージ基板101では、配線構造102の接続電極102bを露出するようにソルダーレジスト103に形成された開口103aを埋め込む接続部104が形成され、接続部104にハンダバンプが接続される構成を採る。パッケージ基板20は、この接続部104も不要であり、これを有しない構成とされる。
本実施形態による電子デバイスを作製するには、先ず図3(a)に示すように、パッケージ基板20の表面に、フィルム状接着材1を貼付する。
フィルム状接着材1の貼付は、例えば10kPa以下の真空度とされた真空状態において、フィルム状接着材1の粘度が適宜低下する温度、例えば80℃以上の温度、0.5MPa以上の加圧下で行う。これにより、フィルム状接着材1にボイドが発生することのない良好な貼付が可能となる。
工程S1では、図3(b)に示すように、パッケージ基板20の表面に半導体チップ10を位置合せし、パッケージ基板20の裏面に設置した加熱加圧ツール2により加熱及び加圧し、ハンダバンプ14が接続電極22bに当接するように突き合わせる。
工程S1では、図4の工程S1のように、加熱及び加圧を行う。具体的には、先ず2分間程度、フィルム状接着材1の反応開始温度を越える第1の温度T1まで漸次加熱すると共に、第1の荷重W1まで加圧する。第1の温度T1は、ハンダバンプ14の溶融点よりも低い温度である。ここで、フィルム状接着材1は、加熱を開始して反応開始温度までは液状であり、反応開始温度に達してから粘度が増加してゆき、第1の温度T1では半固体状となる。工程S1における初期段階では、フィルム状接着材1への荷重伝達の速度に比べて温度増加の速度は遅いため、フィルム状接着材1が液状のままで加熱加圧ツール2からの圧力はハンダバンプ14に伝達する。従って、ハンダバンプ14を所期の高さに潰すことができる。図3(b)では、ハンダバンプ14が加圧で変形する直前の様子を例示している。第1の温度T1に達すると共に第1の荷重W1に達した後は、第1の温度T1及び第1の荷重W1を維持する。
工程S2では、第1の温度T1を維持して、第1の荷重Wより低い第2の荷重W2まで除荷する。工程S2では、フィルム状接着材1は、工程S1における後半の第1の温度T1の加熱と合せた加熱により、半固体状を維持する。
工程S3では、第2の荷重W2を維持して、ハンダバンプ14の溶融点よりも高い温度である第2の温度T2まで昇温して加熱する。このとき、図3(c)に示すように、フィルム状接着材1が半固体状を維持したままハンダバンプ14が溶融し、横長の楕円体形状であるハンダバンプ14により半導体チップ10とパッケージ基板20とが接合される。フィルム状接着材1は、当該接合後には常温まで温度が低下し、固体状となる。
半導体チップ10とパッケージ基板20とが、電極パッド12aと接続電極22bとの間をハンダバンプ14により接続することにより、接合されている。
この信頼性試験では、吸湿リフロー(Moisture Sensitivity Level:MSL)の後に、温度サイクル(Deep Thermal Cycle:DTC)試験を行った。MSLは、JDEC Level3(30℃/60%RH−196時間後にリフロー Max260℃×3回)で行った。DTC試験は、−55℃/125℃で行い、1000cycで不良無しが確認された。図7のように、本実施形態による半導体デバイスでは、信頼性試験の全体を通して安定した抵抗値を示すことが判った。
本実施形態では、電子デバイスとして、第1の実施形態による半導体デバイスの構造を有するチップ内蔵基板を例示する。第1の実施形態の半導体デバイスと対応する構成部材等については、同符号を付して詳しい説明を省略する。
図8は、第2の実施形態によるチップ内蔵基板の構成を示す概略断面図である。
基体30は、第1の実施形態のパッケージ基板20に対応しており、ポリイミド等の基板31と、配線22a及び接続電極22bを有する配線構造22とを備えている。
半導体デバイスは、半導体チップ10と基体30とが、電極パッド12aと接続電極22bとをハンダバンプ14で接続することにより、電気的及び機械的に接合されてなる。半導体チップ10と基体30との間には、横長の楕円体形状のハンダバンプ14及び接続電極22bを直接的に覆い、両者間を充填する接着材が設けられている。この接着材には、フィルム状接着材1が用いられる。当該半導体デバイスは、第1の実施形態で説明した図3の諸工程により作製される。
前記パッケージ基板上にフィルム状接着材を貼付する第1の工程と、
前記第1の工程の後、前記電子部品と前記パッケージ基板とを前記バンプを介して突き合せ、前記フィルム状接着材の反応開始温度よりも高く且つ前記バンプの溶融点よりも低い第1の温度まで昇温しながら第1の荷重まで載荷する第2の工程と、
前記第2の工程の後、前記第1の温度を維持して、前記第1の荷重より低い第2の荷重まで除荷する第3の工程と、
前記第3の工程の後、前記第2の荷重を維持して、前記バンプの溶融点以上の第2の温度まで昇温する第4の工程と
を含むことを特徴とする電子デバイスの製造方法。
前記バンプと、前記バンプが接続される前記パッケージ基板の接続電極とを直接的に覆い、前記電子部品と前記パッケージ基板との間を充填する接着材を備えたことを特徴とする電子デバイス。
2 加熱加圧ツール
10 半導体チップ
11 半導体基板
12 素子層
12a 電極パッド
13 保護層
14 ハンダバンプ
20,101 パッケージ基板
21,31 基板
22,102 配線構造
22a,102a 配線
22b,102b 接続電極
30 基体
32,43 フィルドビア
41 受動素子
42 樹脂
44,45 配線層
103 ソルダーレジスト
103a 開口
104 接続部
Claims (4)
- 電子部品とパッケージ基板とがバンプにより接合されてなる電子デバイスの製造方法であって、
前記パッケージ基板上にフィルム状接着材を貼付する第1の工程と、
前記第1の工程の後、前記電子部品と前記パッケージ基板とを前記バンプを介して突き合せ、前記フィルム状接着材の反応開始温度よりも高く且つ前記バンプの溶融点よりも低い第1の温度まで昇温しながら第1の荷重まで載荷する第2の工程と、
前記第2の工程の後、前記第1の温度を維持して、前記第1の荷重より低い第2の荷重まで除荷する第3の工程と、
前記第3の工程の後、前記第2の荷重を維持して、前記バンプの溶融点以上の第2の温度まで昇温する第4の工程と
を含み、
前記フィルム状接着材は、フラックス成分として酸無水物及び有機酸の少なくとも1種を含有し、常温では固体状であり、前記第1の温度よりも低い反応開始温度に達するまでは液状であり、前記第1の温度及び前記第2の温度では半固体状であることを特徴とする電子デバイスの製造方法。 - 前記フィルム状接着材は、前記バンプと、前記バンプが接続される前記パッケージ基板の接続電極とを直接的に覆い、前記電子部品と前記パッケージ基板との間を充填することを特徴とする請求項1に記載の電子デバイスの製造方法。
- 前記接続電極は、その幅が前記バンプの幅よりも狭いことを特徴とする請求項2に記載の電子デバイスの製造方法。
- 前記バンプは、横長の楕円体形状となることを特徴とする請求項1〜3のいずれか1項に記載の電子デバイスの製造方法。
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