JP6092555B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP6092555B2
JP6092555B2 JP2012209398A JP2012209398A JP6092555B2 JP 6092555 B2 JP6092555 B2 JP 6092555B2 JP 2012209398 A JP2012209398 A JP 2012209398A JP 2012209398 A JP2012209398 A JP 2012209398A JP 6092555 B2 JP6092555 B2 JP 6092555B2
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JP
Japan
Prior art keywords
layer
wiring
wiring layer
insulating layer
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012209398A
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English (en)
Japanese (ja)
Other versions
JP2014063950A (ja
JP2014063950A5 (enExample
Inventor
小林　和弘
和弘 小林
幸太郎 小谷
幸太郎 小谷
中村　順一
順一 中村
金子　健太郎
健太郎 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012209398A priority Critical patent/JP6092555B2/ja
Priority to US14/027,648 priority patent/US9006103B2/en
Publication of JP2014063950A publication Critical patent/JP2014063950A/ja
Publication of JP2014063950A5 publication Critical patent/JP2014063950A5/ja
Application granted granted Critical
Publication of JP6092555B2 publication Critical patent/JP6092555B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012209398A 2012-09-24 2012-09-24 配線基板の製造方法 Active JP6092555B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012209398A JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法
US14/027,648 US9006103B2 (en) 2012-09-24 2013-09-16 Method of manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012209398A JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2014063950A JP2014063950A (ja) 2014-04-10
JP2014063950A5 JP2014063950A5 (enExample) 2015-09-24
JP6092555B2 true JP6092555B2 (ja) 2017-03-08

Family

ID=50339249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012209398A Active JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法

Country Status (2)

Country Link
US (1) US9006103B2 (enExample)
JP (1) JP6092555B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017141985A1 (ja) 2016-02-18 2017-08-24 三井金属鉱業株式会社 プリント配線板製造用銅箔、キャリア付銅箔及び銅張積層板、並びにそれらを用いたプリント配線板の製造方法
WO2017141983A1 (ja) 2016-02-18 2017-08-24 三井金属鉱業株式会社 プリント配線板の製造方法
US10096542B2 (en) * 2017-02-22 2018-10-09 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package structure and manufacturing process
WO2019082795A1 (ja) * 2017-10-26 2019-05-02 三井金属鉱業株式会社 極薄銅箔及びキャリア付極薄銅箔、並びにプリント配線板の製造方法
TWI751554B (zh) * 2020-05-12 2022-01-01 台灣愛司帝科技股份有限公司 影像顯示器及其拼接式電路承載與控制模組
KR102921306B1 (ko) * 2021-02-15 2026-02-02 삼성전자주식회사 배선 구조체를 포함하는 집적회로 칩
TW202410319A (zh) * 2022-08-26 2024-03-01 日商Ｍｇｃ電子科技股份有限公司 積層體、及無芯基板之製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008228A (ja) * 2001-06-22 2003-01-10 Ibiden Co Ltd 多層プリント配線板およびその製造方法
JP2007059821A (ja) * 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP5092547B2 (ja) 2007-05-30 2012-12-05 凸版印刷株式会社 印刷配線板の製造方法
JP5092662B2 (ja) 2007-10-03 2012-12-05 凸版印刷株式会社 印刷配線板の製造方法
JP5479073B2 (ja) * 2009-12-21 2014-04-23 新光電気工業株式会社 配線基板及びその製造方法
JP5603600B2 (ja) * 2010-01-13 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
JP2011199077A (ja) * 2010-03-19 2011-10-06 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
US8319318B2 (en) * 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages

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Publication number Publication date
JP2014063950A (ja) 2014-04-10
US20140087556A1 (en) 2014-03-27
US9006103B2 (en) 2015-04-14

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