JP6092555B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP6092555B2
JP6092555B2 JP2012209398A JP2012209398A JP6092555B2 JP 6092555 B2 JP6092555 B2 JP 6092555B2 JP 2012209398 A JP2012209398 A JP 2012209398A JP 2012209398 A JP2012209398 A JP 2012209398A JP 6092555 B2 JP6092555 B2 JP 6092555B2
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JP
Japan
Prior art keywords
layer
wiring
wiring layer
insulating layer
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012209398A
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English (en)
Japanese (ja)
Other versions
JP2014063950A (ja
JP2014063950A5 (enExample
Inventor
小林　和弘
和弘 小林
幸太郎 小谷
幸太郎 小谷
中村　順一
順一 中村
金子　健太郎
健太郎 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012209398A priority Critical patent/JP6092555B2/ja
Priority to US14/027,648 priority patent/US9006103B2/en
Publication of JP2014063950A publication Critical patent/JP2014063950A/ja
Publication of JP2014063950A5 publication Critical patent/JP2014063950A5/ja
Application granted granted Critical
Publication of JP6092555B2 publication Critical patent/JP6092555B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012209398A 2012-09-24 2012-09-24 配線基板の製造方法 Active JP6092555B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012209398A JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法
US14/027,648 US9006103B2 (en) 2012-09-24 2013-09-16 Method of manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012209398A JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2014063950A JP2014063950A (ja) 2014-04-10
JP2014063950A5 JP2014063950A5 (enExample) 2015-09-24
JP6092555B2 true JP6092555B2 (ja) 2017-03-08

Family

ID=50339249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012209398A Active JP6092555B2 (ja) 2012-09-24 2012-09-24 配線基板の製造方法

Country Status (2)

Country Link
US (1) US9006103B2 (enExample)
JP (1) JP6092555B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6836580B2 (ja) 2016-02-18 2021-03-03 三井金属鉱業株式会社 プリント配線板製造用銅箔、キャリア付銅箔及び銅張積層板、並びにそれらを用いたプリント配線板の製造方法
KR102746877B1 (ko) 2016-02-18 2024-12-27 미쓰이금속광업주식회사 프린트 배선판의 제조 방법
US10096542B2 (en) * 2017-02-22 2018-10-09 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package structure and manufacturing process
CN110997313A (zh) * 2017-10-26 2020-04-10 三井金属矿业株式会社 极薄铜箔和带载体的极薄铜箔、以及印刷电路板的制造方法
TWI751554B (zh) * 2020-05-12 2022-01-01 台灣愛司帝科技股份有限公司 影像顯示器及其拼接式電路承載與控制模組
KR20220116623A (ko) * 2021-02-15 2022-08-23 삼성전자주식회사 배선 구조체를 포함하는 집적회로 칩
TW202410319A (zh) * 2022-08-26 2024-03-01 日商Ｍｇｃ電子科技股份有限公司 積層體、及無芯基板之製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008228A (ja) * 2001-06-22 2003-01-10 Ibiden Co Ltd 多層プリント配線板およびその製造方法
JP2007059821A (ja) * 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP5092547B2 (ja) 2007-05-30 2012-12-05 凸版印刷株式会社 印刷配線板の製造方法
JP5092662B2 (ja) 2007-10-03 2012-12-05 凸版印刷株式会社 印刷配線板の製造方法
JP5479073B2 (ja) * 2009-12-21 2014-04-23 新光電気工業株式会社 配線基板及びその製造方法
JP5603600B2 (ja) * 2010-01-13 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
JP2011199077A (ja) * 2010-03-19 2011-10-06 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
US8319318B2 (en) * 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages

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Publication number Publication date
US20140087556A1 (en) 2014-03-27
JP2014063950A (ja) 2014-04-10
US9006103B2 (en) 2015-04-14

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