JP6058806B2 - ベクトルレジスタファイルの素子バンクに対するアドレスラインの選択的な結合 - Google Patents

ベクトルレジスタファイルの素子バンクに対するアドレスラインの選択的な結合 Download PDF

Info

Publication number
JP6058806B2
JP6058806B2 JP2015537735A JP2015537735A JP6058806B2 JP 6058806 B2 JP6058806 B2 JP 6058806B2 JP 2015537735 A JP2015537735 A JP 2015537735A JP 2015537735 A JP2015537735 A JP 2015537735A JP 6058806 B2 JP6058806 B2 JP 6058806B2
Authority
JP
Japan
Prior art keywords
address
hardware element
address line
address lines
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015537735A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016500877A5 (enExample
JP2016500877A (ja
Inventor
アジャイ・アナント・イングル
マーク・エム・ホフマン
ディーパック・マシュー
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016500877A publication Critical patent/JP2016500877A/ja
Publication of JP2016500877A5 publication Critical patent/JP2016500877A5/ja
Application granted granted Critical
Publication of JP6058806B2 publication Critical patent/JP6058806B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Static Random-Access Memory (AREA)
JP2015537735A 2012-10-18 2013-10-09 ベクトルレジスタファイルの素子バンクに対するアドレスラインの選択的な結合 Expired - Fee Related JP6058806B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/654,730 US9268571B2 (en) 2012-10-18 2012-10-18 Selective coupling of an address line to an element bank of a vector register file
US13/654,730 2012-10-18
PCT/US2013/064063 WO2014062445A1 (en) 2012-10-18 2013-10-09 Selective coupling of an address line to an element bank of a vector register file

Publications (3)

Publication Number Publication Date
JP2016500877A JP2016500877A (ja) 2016-01-14
JP2016500877A5 JP2016500877A5 (enExample) 2016-06-02
JP6058806B2 true JP6058806B2 (ja) 2017-01-11

Family

ID=49484456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015537735A Expired - Fee Related JP6058806B2 (ja) 2012-10-18 2013-10-09 ベクトルレジスタファイルの素子バンクに対するアドレスラインの選択的な結合

Country Status (6)

Country Link
US (1) US9268571B2 (enExample)
EP (1) EP2909713B1 (enExample)
JP (1) JP6058806B2 (enExample)
KR (1) KR101635116B1 (enExample)
CN (1) CN104685465B (enExample)
WO (1) WO2014062445A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136842B2 (en) 2013-06-07 2015-09-15 Altera Corporation Integrated circuit device with embedded programmable logic
US10236043B2 (en) * 2016-06-06 2019-03-19 Altera Corporation Emulated multiport memory element circuitry with exclusive-OR based control circuitry
GB2552154B (en) * 2016-07-08 2019-03-06 Advanced Risc Mach Ltd Vector register access
US10162752B2 (en) * 2016-09-22 2018-12-25 Qualcomm Incorporated Data storage at contiguous memory addresses
US11048509B2 (en) * 2018-06-05 2021-06-29 Qualcomm Incorporated Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
US10930366B2 (en) * 2019-07-17 2021-02-23 Micron Technology, Inc. Storage device with test interface
US12183412B2 (en) 2020-09-25 2024-12-31 Altera Corporation Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device
CN115269199B (zh) * 2022-08-11 2025-09-05 北京奕斯伟计算技术股份有限公司 数据处理方法、装置、电子设备及计算机可读存储介质

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61241870A (ja) * 1985-04-19 1986-10-28 Hitachi Ltd ベクトルプロセツサ
US4980817A (en) 1987-08-31 1990-12-25 Digital Equipment Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports
EP0814411A3 (en) * 1988-06-07 1998-03-04 Fujitsu Limited Vector data processing apparatus
JP2941817B2 (ja) 1988-09-14 1999-08-30 株式会社日立製作所 ベクトル処理装置
JPH0452760A (ja) * 1990-06-14 1992-02-20 Koufu Nippon Denki Kk ベクトル処理装置
JP2625277B2 (ja) * 1991-05-20 1997-07-02 富士通株式会社 メモリアクセス装置
JPH06274528A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd ベクトル演算処理装置
US5832290A (en) * 1994-06-13 1998-11-03 Hewlett-Packard Co. Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems
US5922066A (en) * 1997-02-24 1999-07-13 Samsung Electronics Co., Ltd. Multifunction data aligner in wide data width processor
JPH11184674A (ja) 1997-12-24 1999-07-09 Fujitsu Ltd レジスタファイル
US6665790B1 (en) * 2000-02-29 2003-12-16 International Business Machines Corporation Vector register file with arbitrary vector addressing
JP3779540B2 (ja) 2000-11-08 2006-05-31 株式会社ルネサステクノロジ 複数レジスタ指定が可能なｓｉｍｄ演算方式
US20110087859A1 (en) * 2002-02-04 2011-04-14 Mimar Tibet System cycle loading and storing of misaligned vector elements in a simd processor
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7284113B2 (en) * 2003-01-29 2007-10-16 Via Technologies, Inc. Synchronous periodical orthogonal data converter
GB2409065B (en) * 2003-12-09 2006-10-25 Advanced Risc Mach Ltd Multiplexing operations in SIMD processing
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
US20060259737A1 (en) * 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Vector processor with special purpose registers and high speed memory access
US20070150697A1 (en) * 2005-05-10 2007-06-28 Telairity Semiconductor, Inc. Vector processor with multi-pipe vector block matching
US7750915B1 (en) 2005-12-19 2010-07-06 Nvidia Corporation Concurrent access of data elements stored across multiple banks in a shared memory resource
ATE494582T1 (de) 2006-05-16 2011-01-15 Nxp Bv Speicherarchitektur
US20080291208A1 (en) 2007-05-24 2008-11-27 Gary Keall Method and system for processing data via a 3d pipeline coupled to a generic video processing unit
US8108652B1 (en) * 2007-09-13 2012-01-31 Ronald Chi-Chun Hui Vector processing with high execution throughput
US20110320765A1 (en) 2010-06-28 2011-12-29 International Business Machines Corporation Variable width vector instruction processor
US20120110037A1 (en) 2010-11-01 2012-05-03 Qualcomm Incorporated Methods and Apparatus for a Read, Merge and Write Register File

Also Published As

Publication number Publication date
WO2014062445A1 (en) 2014-04-24
KR20150070302A (ko) 2015-06-24
US20140115227A1 (en) 2014-04-24
KR101635116B1 (ko) 2016-06-30
JP2016500877A (ja) 2016-01-14
EP2909713B1 (en) 2017-07-05
CN104685465B (zh) 2018-05-01
US9268571B2 (en) 2016-02-23
CN104685465A (zh) 2015-06-03
EP2909713A1 (en) 2015-08-26

Similar Documents

Publication Publication Date Title
JP6058806B2 (ja) ベクトルレジスタファイルの素子バンクに対するアドレスラインの選択的な結合
US9342479B2 (en) Systems and methods of data extraction in a vector processor
US10311127B2 (en) Sparse matrix vector multiplication
EP3033670A1 (en) Vector accumulation method and apparatus
CN103473232B (zh) 应用程序的自主管理装置及其方法
JP2010539598A (ja) ｎ−ウェイキャッシュを用いるシステムおよび方法
US20160328325A1 (en) Reconfigurable fetch pipeline
JP2016522936A (ja) データアクセスの前のメモリ内の不完全データエントリから冗長データエントリへのデータのリダイレクトならびに関連するシステムおよび方法
KR20240112980A (ko) 벡터 셔플 방법, 프로세서 및 전자기기
US9721625B2 (en) Time-constrained data copying between storage media
US20170046168A1 (en) Scalable single-instruction-multiple-data instructions
US11243649B2 (en) Method and apparatus for providing web browsing interface including dividing the content display region into at least two spaces, and allowing selection of different modes for loading web pages ot the at elast two spaces
CN108763549A (zh) 公交线路的快速查询方法、装置、终端设备及存储介质
EP2524315A1 (en) Multi-stage multiplexing operation including combined selection and data alignment or data replication
KR100710626B1 (ko) 데이터 버스 확장 구조를 갖는 디지털 처리 장치 및 그방법
US12363051B2 (en) Crossbar multipathing for multicast performance in tiled switches
US9501584B2 (en) Apparatus and method for distributing a search key in a ternary memory array
CN106303668A (zh) 一种多媒体播放信息的处理方法、装置及终端
JP6576688B2 (ja) 電子機器および接続制御方法
CN109660610A (zh) 一种数据处理方法、装置、设备及存储介质

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20150415

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160406

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160406

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20160406

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20160630

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160711

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161011

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161207

R150 Certificate of patent or registration of utility model

Ref document number: 6058806

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees