KR101635116B1 - 벡터 레지스터 파일의 엘리먼트 뱅크에의 어드레스 라인의 선택적 커플링 - Google Patents

벡터 레지스터 파일의 엘리먼트 뱅크에의 어드레스 라인의 선택적 커플링 Download PDF

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KR101635116B1
KR101635116B1 KR1020157012568A KR20157012568A KR101635116B1 KR 101635116 B1 KR101635116 B1 KR 101635116B1 KR 1020157012568 A KR1020157012568 A KR 1020157012568A KR 20157012568 A KR20157012568 A KR 20157012568A KR 101635116 B1 KR101635116 B1 KR 101635116B1
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KR20150070302A (ko
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아제이 아난트 잉글
마크 엠. 호프만
디파크 매튜
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Static Random-Access Memory (AREA)
KR1020157012568A 2012-10-18 2013-10-09 벡터 레지스터 파일의 엘리먼트 뱅크에의 어드레스 라인의 선택적 커플링 Expired - Fee Related KR101635116B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/654,730 US9268571B2 (en) 2012-10-18 2012-10-18 Selective coupling of an address line to an element bank of a vector register file
US13/654,730 2012-10-18
PCT/US2013/064063 WO2014062445A1 (en) 2012-10-18 2013-10-09 Selective coupling of an address line to an element bank of a vector register file

Publications (2)

Publication Number Publication Date
KR20150070302A KR20150070302A (ko) 2015-06-24
KR101635116B1 true KR101635116B1 (ko) 2016-06-30

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KR1020157012568A Expired - Fee Related KR101635116B1 (ko) 2012-10-18 2013-10-09 벡터 레지스터 파일의 엘리먼트 뱅크에의 어드레스 라인의 선택적 커플링

Country Status (6)

Country Link
US (1) US9268571B2 (enExample)
EP (1) EP2909713B1 (enExample)
JP (1) JP6058806B2 (enExample)
KR (1) KR101635116B1 (enExample)
CN (1) CN104685465B (enExample)
WO (1) WO2014062445A1 (enExample)

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US9136842B2 (en) 2013-06-07 2015-09-15 Altera Corporation Integrated circuit device with embedded programmable logic
US10236043B2 (en) * 2016-06-06 2019-03-19 Altera Corporation Emulated multiport memory element circuitry with exclusive-OR based control circuitry
GB2552154B (en) * 2016-07-08 2019-03-06 Advanced Risc Mach Ltd Vector register access
US10162752B2 (en) * 2016-09-22 2018-12-25 Qualcomm Incorporated Data storage at contiguous memory addresses
US11048509B2 (en) * 2018-06-05 2021-06-29 Qualcomm Incorporated Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
US10930366B2 (en) * 2019-07-17 2021-02-23 Micron Technology, Inc. Storage device with test interface
US12183412B2 (en) 2020-09-25 2024-12-31 Altera Corporation Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device
CN115269199B (zh) * 2022-08-11 2025-09-05 北京奕斯伟计算技术股份有限公司 数据处理方法、装置、电子设备及计算机可读存储介质

Citations (2)

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US20040103262A1 (en) 2000-02-29 2004-05-27 International Business Machines Corporation Vector register file with arbitrary vector addressing
US20110087859A1 (en) 2002-02-04 2011-04-14 Mimar Tibet System cycle loading and storing of misaligned vector elements in a simd processor

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JPS61241870A (ja) * 1985-04-19 1986-10-28 Hitachi Ltd ベクトルプロセツサ
US4980817A (en) 1987-08-31 1990-12-25 Digital Equipment Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports
DE68928507T2 (de) * 1988-06-07 1998-04-16 Fujitsu Ltd Vektordatenverarbeitungsvorrichtung
JP2941817B2 (ja) 1988-09-14 1999-08-30 株式会社日立製作所 ベクトル処理装置
JPH0452760A (ja) * 1990-06-14 1992-02-20 Koufu Nippon Denki Kk ベクトル処理装置
JP2625277B2 (ja) * 1991-05-20 1997-07-02 富士通株式会社 メモリアクセス装置
JPH06274528A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd ベクトル演算処理装置
US5832290A (en) * 1994-06-13 1998-11-03 Hewlett-Packard Co. Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems
US5922066A (en) * 1997-02-24 1999-07-13 Samsung Electronics Co., Ltd. Multifunction data aligner in wide data width processor
JPH11184674A (ja) 1997-12-24 1999-07-09 Fujitsu Ltd レジスタファイル
JP3779540B2 (ja) 2000-11-08 2006-05-31 株式会社ルネサステクノロジ 複数レジスタ指定が可能なｓｉｍｄ演算方式
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7284113B2 (en) * 2003-01-29 2007-10-16 Via Technologies, Inc. Synchronous periodical orthogonal data converter
GB2409065B (en) * 2003-12-09 2006-10-25 Advanced Risc Mach Ltd Multiplexing operations in SIMD processing
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
US20070150697A1 (en) * 2005-05-10 2007-06-28 Telairity Semiconductor, Inc. Vector processor with multi-pipe vector block matching
US20060259737A1 (en) * 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Vector processor with special purpose registers and high speed memory access
US7750915B1 (en) 2005-12-19 2010-07-06 Nvidia Corporation Concurrent access of data elements stored across multiple banks in a shared memory resource
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US20080291208A1 (en) 2007-05-24 2008-11-27 Gary Keall Method and system for processing data via a 3d pipeline coupled to a generic video processing unit
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Publication number Priority date Publication date Assignee Title
US20040103262A1 (en) 2000-02-29 2004-05-27 International Business Machines Corporation Vector register file with arbitrary vector addressing
US20110087859A1 (en) 2002-02-04 2011-04-14 Mimar Tibet System cycle loading and storing of misaligned vector elements in a simd processor

Also Published As

Publication number Publication date
WO2014062445A1 (en) 2014-04-24
CN104685465B (zh) 2018-05-01
EP2909713A1 (en) 2015-08-26
JP2016500877A (ja) 2016-01-14
JP6058806B2 (ja) 2017-01-11
EP2909713B1 (en) 2017-07-05
US20140115227A1 (en) 2014-04-24
KR20150070302A (ko) 2015-06-24
CN104685465A (zh) 2015-06-03
US9268571B2 (en) 2016-02-23

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