JP6043015B2 - コントローラ及びメモリのスタックを備えたフレキシブルなメモリシステム - Google Patents

コントローラ及びメモリのスタックを備えたフレキシブルなメモリシステム Download PDF

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JP6043015B2
JP6043015B2 JP2016500737A JP2016500737A JP6043015B2 JP 6043015 B2 JP6043015 B2 JP 6043015B2 JP 2016500737 A JP2016500737 A JP 2016500737A JP 2016500737 A JP2016500737 A JP 2016500737A JP 6043015 B2 JP6043015 B2 JP 6043015B2
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memory
vault
vaults
memory system
stack
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JP2016512360A (ja
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エム． ジェデロー，ジョセフ
エム． ジェデロー，ジョセフ
キース，ブレント
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マイクロン テクノロジー， インク．
マイクロン テクノロジー， インク．
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2016500737A 2013-03-15 2014-03-06 コントローラ及びメモリのスタックを備えたフレキシブルなメモリシステム Active JP6043015B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361791182P 2013-03-15 2013-03-15
US61/791,182 2013-03-15
US13/919,503 2013-06-17
US13/919,503 US9679615B2 (en) 2013-03-15 2013-06-17 Flexible memory system with a controller and a stack of memory
PCT/US2014/021211 WO2014149851A1 (en) 2013-03-15 2014-03-06 Flexible memory system with a controller and a stack of memory

Publications (2)

Publication Number Publication Date
JP2016512360A JP2016512360A (ja) 2016-04-25
JP6043015B2 true JP6043015B2 (ja) 2016-12-14

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JP2016500737A Active JP6043015B2 (ja) 2013-03-15 2014-03-06 コントローラ及びメモリのスタックを備えたフレキシブルなメモリシステム

Country Status (7)

Country Link
US (6) US9679615B2 (zh)
EP (1) EP2973694B1 (zh)
JP (1) JP6043015B2 (zh)
KR (1) KR101756575B1 (zh)
CN (2) CN109599134B (zh)
TW (2) TWI681525B (zh)
WO (1) WO2014149851A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679615B2 (en) 2013-03-15 2017-06-13 Micron Technology, Inc. Flexible memory system with a controller and a stack of memory
US9819345B2 (en) 2014-10-02 2017-11-14 Altera Corporation Scalable 2.5D interface architecture
KR102338266B1 (ko) * 2015-09-15 2021-12-16 에스케이하이닉스 주식회사 메모리 네트워크 및 이를 포함하는 시스템
US10403604B2 (en) * 2015-11-05 2019-09-03 Intel Corporation Stacked package assembly with voltage reference plane
US10984838B2 (en) * 2015-11-17 2021-04-20 Advanced Micro Devices, Inc. Interconnect architecture for three-dimensional processing systems
US10089178B2 (en) * 2016-02-29 2018-10-02 International Business Machines Corporation Developing an accurate dispersed storage network memory performance model through training
KR20230151553A (ko) * 2016-06-27 2023-11-01 애플 인크. 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템
KR102663810B1 (ko) * 2016-12-30 2024-05-07 삼성전자주식회사 전자 소자 패키지
PL3812900T3 (pl) * 2016-12-31 2024-04-08 Intel Corporation Systemy, sposoby i aparaty do obliczania heterogenicznego
KR20180079811A (ko) 2017-01-02 2018-07-11 삼성전자주식회사 메모리 소자의 dq 패드를 재구성하는 방법 및 dq 패드 재구성이 가능한 메모리 장치
US11397687B2 (en) 2017-01-25 2022-07-26 Samsung Electronics Co., Ltd. Flash-integrated high bandwidth memory appliance
KR102482896B1 (ko) 2017-12-28 2022-12-30 삼성전자주식회사 이종 휘발성 메모리 칩들을 포함하는 메모리 장치 및 이를 포함하는 전자 장치
EP3853850A4 (en) * 2018-09-20 2022-06-22 Micron Technology, Inc. ROUTING TECHNIQUES FOR STACKED STORAGE
KR20200065762A (ko) * 2018-11-30 2020-06-09 에스케이하이닉스 주식회사 메모리 시스템
US11476241B2 (en) 2019-03-19 2022-10-18 Micron Technology, Inc. Interposer, microelectronic device assembly including same and methods of fabrication
US11251155B2 (en) 2019-05-30 2022-02-15 Samsung Electronics Co., Ltd. Semiconductor package
US11239169B1 (en) 2020-07-24 2022-02-01 Micron Technology, Inc. Semiconductor memory stacks connected to processing units and associated systems and methods

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617681B1 (en) 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP3896112B2 (ja) 2003-12-25 2007-03-22 エルピーダメモリ株式会社 半導体集積回路装置
EP1598868A1 (en) * 2004-05-18 2005-11-23 Texas Instruments Inc. Stacked dies having shared access to memory
EP1643508B1 (en) 2004-10-01 2013-05-22 International Business Machines Corporation Non-volatile memory element with programmable resistance
US7472220B2 (en) 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
EP2005303B1 (en) * 2006-02-09 2012-04-18 Google Inc. Memory circuit system and method
WO2007095080A2 (en) * 2006-02-09 2007-08-23 Metaram, Inc. Memory circuit system and method
KR100772841B1 (ko) * 2006-07-28 2007-11-02 삼성전자주식회사 프로세서들간 호스트 인터페이싱 기능을 갖는 멀티패쓰억세스블 반도체 메모리 장치
JP4878215B2 (ja) * 2006-05-26 2012-02-15 ルネサスエレクトロニクス株式会社 インタフェース回路及びメモリ制御装置
JP4885623B2 (ja) * 2006-06-13 2012-02-29 エルピーダメモリ株式会社 積層半導体装置
KR100855586B1 (ko) * 2006-11-10 2008-09-01 삼성전자주식회사 반도체 메모리 장치 및 그의 레이아웃 방법
US8139432B2 (en) * 2006-12-27 2012-03-20 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
KR100875955B1 (ko) 2007-01-25 2008-12-26 삼성전자주식회사 스택 패키지 및 그의 제조 방법
KR100887417B1 (ko) * 2007-04-11 2009-03-06 삼성전자주식회사 멀티 프로세서 시스템에서 불휘발성 메모리의 공유적사용을 제공하기 위한 멀티패쓰 억세스블 반도체 메모리장치
JP5149554B2 (ja) 2007-07-17 2013-02-20 株式会社日立製作所 半導体装置
US7623365B2 (en) * 2007-08-29 2009-11-24 Micron Technology, Inc. Memory device interface methods, apparatus, and systems
US7889578B2 (en) 2007-10-17 2011-02-15 Mosaid Technologies Incorporated Single-strobe operation of memory devices
US7701252B1 (en) * 2007-11-06 2010-04-20 Altera Corporation Stacked die network-on-chip for FPGA
US9229887B2 (en) 2008-02-19 2016-01-05 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
US7701251B1 (en) * 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
US8060719B2 (en) 2008-05-28 2011-11-15 Micron Technology, Inc. Hybrid memory management
US7855931B2 (en) 2008-07-21 2010-12-21 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
US7978721B2 (en) * 2008-07-02 2011-07-12 Micron Technology Inc. Multi-serial interface stacked-die memory architecture
US8127204B2 (en) * 2008-08-15 2012-02-28 Micron Technology, Inc. Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system
US8254191B2 (en) * 2008-10-30 2012-08-28 Micron Technology, Inc. Switched interface stacked-die memory architecture
US8683164B2 (en) 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
US8364901B2 (en) * 2009-02-13 2013-01-29 Micron Technology, Inc. Memory prefetch systems and methods
US8018752B2 (en) 2009-03-23 2011-09-13 Micron Technology, Inc. Configurable bandwidth memory devices and methods
US8612809B2 (en) 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
US8966208B2 (en) * 2010-02-25 2015-02-24 Conversant Ip Management Inc. Semiconductor memory device with plural memory die and controller die
US9123552B2 (en) * 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
KR101728068B1 (ko) 2010-06-01 2017-04-19 삼성전자 주식회사 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법
KR101854251B1 (ko) 2010-11-30 2018-05-03 삼성전자주식회사 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치
KR20120132287A (ko) 2011-05-27 2012-12-05 삼성전자주식회사 반도체 메모리 장치, 반도체 메모리 패키지 및 반도체 메모리 장치의 집적도 증대 방법
US8933715B2 (en) * 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
US9679615B2 (en) 2013-03-15 2017-06-13 Micron Technology, Inc. Flexible memory system with a controller and a stack of memory
JP5621894B2 (ja) 2013-09-11 2014-11-12 株式会社寺岡精工 携帯端末、および管理装置
KR102282971B1 (ko) * 2014-12-05 2021-07-29 삼성전자주식회사 반도체 메모리 장치, 및 상기 반도체 메모리 장치를 포함하는 메모리 시스템

Also Published As

Publication number Publication date
CN109599134A (zh) 2019-04-09
EP2973694A1 (en) 2016-01-20
US20170352388A1 (en) 2017-12-07
US20190385646A1 (en) 2019-12-19
US11769534B2 (en) 2023-09-26
US20200411064A1 (en) 2020-12-31
EP2973694B1 (en) 2020-05-06
US10283172B2 (en) 2019-05-07
TWI681525B (zh) 2020-01-01
US9679615B2 (en) 2017-06-13
CN109599134B (zh) 2022-12-13
TW201515176A (zh) 2015-04-16
US11450354B2 (en) 2022-09-20
US11031049B2 (en) 2021-06-08
US20210295879A1 (en) 2021-09-23
KR20160040453A (ko) 2016-04-14
US20230080130A1 (en) 2023-03-16
KR101756575B1 (ko) 2017-07-10
CN105144377A (zh) 2015-12-09
WO2014149851A1 (en) 2014-09-25
CN105144377B (zh) 2018-09-25
US10714150B2 (en) 2020-07-14
EP2973694A4 (en) 2016-08-17
US20140281204A1 (en) 2014-09-18
JP2016512360A (ja) 2016-04-25
TW201926612A (zh) 2019-07-01

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