JP6029873B2 - 配線基板、配線基板の製造方法及び半導体装置の製造方法 - Google Patents

配線基板、配線基板の製造方法及び半導体装置の製造方法 Download PDF

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Publication number
JP6029873B2
JP6029873B2 JP2012147389A JP2012147389A JP6029873B2 JP 6029873 B2 JP6029873 B2 JP 6029873B2 JP 2012147389 A JP2012147389 A JP 2012147389A JP 2012147389 A JP2012147389 A JP 2012147389A JP 6029873 B2 JP6029873 B2 JP 6029873B2
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Japan
Prior art keywords
layer
adhesive layer
support substrate
pad
adhesive
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Application number
JP2012147389A
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English (en)
Japanese (ja)
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JP2014011335A (ja
JP2014011335A5 (enExample
Inventor
中村　敦
敦 中村
三喜 今井
三喜 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012147389A priority Critical patent/JP6029873B2/ja
Priority to US13/926,214 priority patent/US8945336B2/en
Publication of JP2014011335A publication Critical patent/JP2014011335A/ja
Publication of JP2014011335A5 publication Critical patent/JP2014011335A5/ja
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012147389A 2012-06-29 2012-06-29 配線基板、配線基板の製造方法及び半導体装置の製造方法 Active JP6029873B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012147389A JP6029873B2 (ja) 2012-06-29 2012-06-29 配線基板、配線基板の製造方法及び半導体装置の製造方法
US13/926,214 US8945336B2 (en) 2012-06-29 2013-06-25 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012147389A JP6029873B2 (ja) 2012-06-29 2012-06-29 配線基板、配線基板の製造方法及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2014011335A JP2014011335A (ja) 2014-01-20
JP2014011335A5 JP2014011335A5 (enExample) 2015-08-06
JP6029873B2 true JP6029873B2 (ja) 2016-11-24

Family

ID=49777270

Family Applications (1)

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JP2012147389A Active JP6029873B2 (ja) 2012-06-29 2012-06-29 配線基板、配線基板の製造方法及び半導体装置の製造方法

Country Status (2)

Country Link
US (1) US8945336B2 (enExample)
JP (1) JP6029873B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185716A (zh) * 2014-02-13 2015-12-23 群成科技股份有限公司 电子封装件、封装载板及两者的制造方法
KR20160001169A (ko) * 2014-06-26 2016-01-06 삼성전자주식회사 마킹층을 포함하는 반도체 패키지
JP2016122802A (ja) * 2014-12-25 2016-07-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017157593A (ja) * 2016-02-29 2017-09-07 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 発光ダイオード、発光ダイオードの製造方法、発光ダイオード表示装置及び発光ダイオード表示装置の製造方法
CN114080088B (zh) * 2020-08-10 2024-05-31 鹏鼎控股(深圳)股份有限公司 电路板及其制备方法
US20230106612A1 (en) * 2021-10-05 2023-04-06 Advanced Semiconductor Engineering, Inc. Method of manufacturing electrical package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1213755A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
JP3529507B2 (ja) * 1995-09-04 2004-05-24 沖電気工業株式会社 半導体装置
JPH10270592A (ja) * 1997-03-24 1998-10-09 Texas Instr Japan Ltd 半導体装置及びその製造方法
JP4103482B2 (ja) * 2002-07-16 2008-06-18 日立化成工業株式会社 半導体搭載基板とそれを用いた半導体パッケージ並びにそれらの製造方法
US7556984B2 (en) * 2005-06-17 2009-07-07 Boardtek Electronics Corp. Package structure of chip and the package method thereof
JP4984502B2 (ja) 2005-11-28 2012-07-25 凸版印刷株式会社 Ｂｇａ型キャリア基板の製造方法及びｂｇａ型キャリア基板
JP2007150099A (ja) * 2005-11-29 2007-06-14 Hitachi Cable Ltd 配線基板及びその製造方法並びに配線基板を用いた電子部品の製造方法及びその装置
US8288869B2 (en) * 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof

Also Published As

Publication number Publication date
JP2014011335A (ja) 2014-01-20
US20140001648A1 (en) 2014-01-02
US8945336B2 (en) 2015-02-03

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