JP6015969B2 - 回路基板の形成方法 - Google Patents
回路基板の形成方法 Download PDFInfo
- Publication number
- JP6015969B2 JP6015969B2 JP2014166328A JP2014166328A JP6015969B2 JP 6015969 B2 JP6015969 B2 JP 6015969B2 JP 2014166328 A JP2014166328 A JP 2014166328A JP 2014166328 A JP2014166328 A JP 2014166328A JP 6015969 B2 JP6015969 B2 JP 6015969B2
- Authority
- JP
- Japan
- Prior art keywords
- negative resist
- opening
- forming
- conductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/38—Treatment before imagewise removal, e.g. prebaking
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0577—Double layer of resist having the same pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0588—Second resist used as pattern over first resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1453—Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
(i)有機材料の性質上、各種パターンの寸法が不安定になりやすい。
(ii)露光及び現像の回数が多く、製造工程が複雑である。
12 導体パターン
14、24 ネガレジスト
16、26 フォトマスク
18、28 遮光領域
22、30 露光されていない領域
23 露光された領域
32、34、35 開口
36 シード層
38 メッキ層
40、44 導電ビア
42 配線層
Claims (6)
- 回路基板の形成方法であって、
(a)基板上に導体パターンを形成するステップと、
(b)導体パターンの形成後の基板上に第1ネガレジストを形成するステップと、
(c)導体パターンの表面上の第1ネガレジストを部分的に露光して未露光領域である第1ビア露光部を形成するステップと、
(d)第1ビア露光部の形成後の基板上に第2ネガレジストを形成するステップと、
(e)第1ビア露光部上の第2ネガレジストを部分的に露光して第1ビア露光部よりも大きな未露光領域である第2ビア露光部を形成するステップと、
(f)第2ビア露光部の形成後の第1ネガレジスト及び第2ネガレジストを現像して導体パターンに至るビア開口を形成するステップと、
(g)ビア開口に導体を充填するステップと、を含み、
前記第1ネガレジスト及び前記第2ネガレジストは、前記回路基板の層間絶縁層として利用される、方法。 - 前記第2ビア露光部を形成するステップ(e)は、同時に前記第1ビア露光部上以外の前記第2ネガレジストを部分的に露光して配線露光部を形成することを含み、
前記導体パターンに至るビア開口を形成するステップ(f)は、同時に前記第2ネガレジストに配線開口を形成することを含み、
前記開口に導体を充填するステップ(g)は、同時に前記配線開口に導体を充填することを含む、請求項1に記載の方法。 - 前記ビア開口に導体を充填するステップ(g)は、
前記ビア開口内及び前記ビア開口を除く前記基板の表面にシード層を形成するステップと、
前記シード層上に電解メッキにより導体層を形成するステップと、
前記基板の表面を研磨して前記ビア開口のみに前記導体を残すステップと、を含む請求項1に記載の方法。 - 前記ビア開口に導体を充填するステップ(g)は、
前記ビア開口内、前記配線開口内、及び前記ビア開口と前記配線開口を除く前記基板の表面にシード層を形成するステップと、
前記シード層上に電解メッキにより導体層を形成するステップと、
前記基板の表面を研磨して前記ビア開口及び前記配線開口のみに前記導体を残すステップと、を含む請求項2に記載の方法。 - 前記第1ビア露光部を形成するステップ(c)は、前記第1ネガレジストをレーザで直接露光することを含む、請求項1〜4のいずれか1項に記載の方法
- 前記基板は有機基板であり、前記回路基板はインターポーザとして利用可能である、請求項1〜5のいずれか1項に記載の方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014166328A JP6015969B2 (ja) | 2014-08-19 | 2014-08-19 | 回路基板の形成方法 |
US14/817,378 US9684237B2 (en) | 2014-08-19 | 2015-08-04 | Circuit board formation using organic substrates |
US14/950,673 US9760002B2 (en) | 2014-08-19 | 2015-11-24 | Circuit board formation using organic substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014166328A JP6015969B2 (ja) | 2014-08-19 | 2014-08-19 | 回路基板の形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016042543A JP2016042543A (ja) | 2016-03-31 |
JP6015969B2 true JP6015969B2 (ja) | 2016-10-26 |
Family
ID=55349561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014166328A Expired - Fee Related JP6015969B2 (ja) | 2014-08-19 | 2014-08-19 | 回路基板の形成方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US9684237B2 (ja) |
JP (1) | JP6015969B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102356809B1 (ko) * | 2014-12-26 | 2022-01-28 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR102579880B1 (ko) * | 2016-05-12 | 2023-09-18 | 삼성전자주식회사 | 인터포저, 반도체 패키지, 및 인터포저의 제조 방법 |
CN109037038A (zh) * | 2017-06-08 | 2018-12-18 | 联华电子股份有限公司 | 半导体装置的形成方法 |
KR102321438B1 (ko) * | 2017-07-28 | 2021-11-04 | 엘지이노텍 주식회사 | 인쇄회로기판 |
JP2019062113A (ja) * | 2017-09-27 | 2019-04-18 | 日立化成株式会社 | 配線層の製造方法 |
CN109935515B (zh) | 2017-12-18 | 2021-07-13 | 联华电子股份有限公司 | 形成图形的方法 |
JP7211156B2 (ja) * | 2019-02-27 | 2023-01-24 | 凸版印刷株式会社 | 多層配線基板の製造方法および多層配線基板 |
JP7521258B2 (ja) | 2020-05-26 | 2024-07-24 | Toppanホールディングス株式会社 | 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法 |
US11315890B2 (en) * | 2020-08-11 | 2022-04-26 | Applied Materials, Inc. | Methods of forming microvias with reduced diameter |
Family Cites Families (14)
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US4631111A (en) * | 1984-11-27 | 1986-12-23 | E. I. Du Pont De Nemours And Company | Dichromic process for preparation of conductive circuit |
US4572764A (en) * | 1984-12-13 | 1986-02-25 | E. I. Du Pont De Nemours And Company | Preparation of photoformed plastic multistrate by via formation first |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US5266446A (en) * | 1990-11-15 | 1993-11-30 | International Business Machines Corporation | Method of making a multilayer thin film structure |
US5480048A (en) * | 1992-09-04 | 1996-01-02 | Hitachi, Ltd. | Multilayer wiring board fabricating method |
JP3843154B2 (ja) * | 1996-09-25 | 2006-11-08 | 関西ペイント株式会社 | 光重合性組成物 |
JP2001284813A (ja) * | 2000-03-31 | 2001-10-12 | Mitsubishi Electric Corp | 多層配線板の製造方法 |
JP2003013313A (ja) | 2001-07-02 | 2003-01-15 | Toray Ind Inc | 保温手袋 |
JP3810309B2 (ja) * | 2001-12-03 | 2006-08-16 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4023236B2 (ja) | 2002-07-08 | 2007-12-19 | 松下電器産業株式会社 | 金属配線の形成方法 |
JP2009094412A (ja) * | 2007-10-11 | 2009-04-30 | Sumitomo Chemical Co Ltd | 配線基板の製造方法、表示装置および薄膜能動素子基板 |
US8230592B2 (en) * | 2008-08-19 | 2012-07-31 | International Business Machines Corporation | Method for via stub elimination |
JP5560775B2 (ja) * | 2009-05-20 | 2014-07-30 | 富士通株式会社 | 回路基板及びその製造方法 |
US8536031B2 (en) | 2010-02-19 | 2013-09-17 | International Business Machines Corporation | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme |
-
2014
- 2014-08-19 JP JP2014166328A patent/JP6015969B2/ja not_active Expired - Fee Related
-
2015
- 2015-08-04 US US14/817,378 patent/US9684237B2/en not_active Expired - Fee Related
- 2015-11-24 US US14/950,673 patent/US9760002B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2016042543A (ja) | 2016-03-31 |
US20160081187A1 (en) | 2016-03-17 |
US20160057857A1 (en) | 2016-02-25 |
US9760002B2 (en) | 2017-09-12 |
US9684237B2 (en) | 2017-06-20 |
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