JP5993248B2 - 電子部品内蔵基板及びその製造方法 - Google Patents

電子部品内蔵基板及びその製造方法 Download PDF

Info

Publication number
JP5993248B2
JP5993248B2 JP2012186065A JP2012186065A JP5993248B2 JP 5993248 B2 JP5993248 B2 JP 5993248B2 JP 2012186065 A JP2012186065 A JP 2012186065A JP 2012186065 A JP2012186065 A JP 2012186065A JP 5993248 B2 JP5993248 B2 JP 5993248B2
Authority
JP
Japan
Prior art keywords
wiring board
electronic component
substrate
intermediate wiring
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012186065A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014045051A5 (https=
JP2014045051A (ja
Inventor
倉嶋　信幸
信幸 倉嶋
鉄也 小山
鉄也 小山
肇 飯塚
肇 飯塚
功一 田中
功一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012186065A priority Critical patent/JP5993248B2/ja
Priority to US13/944,188 priority patent/US9059088B2/en
Publication of JP2014045051A publication Critical patent/JP2014045051A/ja
Publication of JP2014045051A5 publication Critical patent/JP2014045051A5/ja
Application granted granted Critical
Publication of JP5993248B2 publication Critical patent/JP5993248B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H05K1/186—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1327—Moulding over PCB locally or completely
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
JP2012186065A 2012-08-27 2012-08-27 電子部品内蔵基板及びその製造方法 Active JP5993248B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012186065A JP5993248B2 (ja) 2012-08-27 2012-08-27 電子部品内蔵基板及びその製造方法
US13/944,188 US9059088B2 (en) 2012-08-27 2013-07-17 Electronic component built-in substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012186065A JP5993248B2 (ja) 2012-08-27 2012-08-27 電子部品内蔵基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2014045051A JP2014045051A (ja) 2014-03-13
JP2014045051A5 JP2014045051A5 (https=) 2015-09-03
JP5993248B2 true JP5993248B2 (ja) 2016-09-14

Family

ID=50147293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012186065A Active JP5993248B2 (ja) 2012-08-27 2012-08-27 電子部品内蔵基板及びその製造方法

Country Status (2)

Country Link
US (1) US9059088B2 (https=)
JP (1) JP5993248B2 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293426B2 (en) 2012-09-28 2016-03-22 Intel Corporation Land side and die side cavities to reduce package Z-height
US9355898B2 (en) 2014-07-30 2016-05-31 Qualcomm Incorporated Package on package (PoP) integrated device comprising a plurality of solder resist layers
JP2016076514A (ja) * 2014-10-02 2016-05-12 大日本印刷株式会社 配線板、電子モジュール
US10181410B2 (en) * 2015-02-27 2019-01-15 Qualcomm Incorporated Integrated circuit package comprising surface capacitor and ground plane
JP6591909B2 (ja) * 2015-07-27 2019-10-16 京セラ株式会社 アンテナモジュール
JP6570924B2 (ja) * 2015-08-31 2019-09-04 新光電気工業株式会社 電子部品装置及びその製造方法
JP2017050315A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP2017050313A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP6806520B2 (ja) * 2016-10-17 2021-01-06 ラピスセミコンダクタ株式会社 半導体装置および配線基板の設計方法
US20200020624A1 (en) * 2018-07-10 2020-01-16 Qualcomm Incorporated Substrate-embedded substrate
US10790162B2 (en) 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102019117844A1 (de) 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
US10796976B2 (en) 2018-10-31 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US11342316B2 (en) * 2020-01-16 2022-05-24 Mediatek Inc. Semiconductor package
JP7421357B2 (ja) 2020-02-05 2024-01-24 新光電気工業株式会社 部品内蔵基板及び部品内蔵基板の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210954A (ja) 2000-01-24 2001-08-03 Ibiden Co Ltd 多層基板
JP2001267710A (ja) * 2000-03-15 2001-09-28 Sony Corp 電子回路装置および多層プリント配線板
JP4372407B2 (ja) 2002-11-12 2009-11-25 イビデン株式会社 多層プリント配線板
JP3879853B2 (ja) * 2003-10-10 2007-02-14 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
JP4182140B2 (ja) 2005-12-14 2008-11-19 新光電気工業株式会社 チップ内蔵基板
JP4901458B2 (ja) * 2006-12-26 2012-03-21 新光電気工業株式会社 電子部品内蔵基板

Also Published As

Publication number Publication date
US9059088B2 (en) 2015-06-16
US20140054773A1 (en) 2014-02-27
JP2014045051A (ja) 2014-03-13

Similar Documents

Publication Publication Date Title
JP5993248B2 (ja) 電子部品内蔵基板及びその製造方法
JP5598787B2 (ja) 積層型半導体装置の製造方法
US6489687B1 (en) Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment
CN102789991B (zh) 封装结构及其制作方法
JP6489965B2 (ja) 電子部品装置及びその製造方法
JP5893387B2 (ja) 電子装置及びその製造方法
JP2014045051A5 (https=)
JP2008218979A (ja) 電子パッケージ及びその製造方法
JP2011249759A (ja) 電子素子内蔵印刷回路基板及びその製造方法
JPWO2007072616A1 (ja) 部品内蔵モジュールおよびその製造方法
JP2013236039A (ja) 半導体装置
US7400048B2 (en) Void-free circuit board and semiconductor package having the same
JP6511851B2 (ja) 多層回路基板、半導体装置、多層回路基板の製造方法
US9293405B2 (en) Semiconductor device
JP2013521654A (ja) 組み込まれたダイを有する集積回路パッケージの熱ビア
US9265147B2 (en) Multi-layer wiring board
JP2009135391A (ja) 電子装置およびその製造方法
US20100127382A1 (en) Semiconductor device
JP2008218758A (ja) 電子回路実装構造体
JP2010272563A (ja) 部品内蔵配線板、部品内蔵配線板の製造方法
TWI433278B (zh) 無承載板之封裝件及其製法
JP2014103244A (ja) 半導体装置および半導体チップ
JP2009266972A (ja) 積層型半導体モジュール及びその製造方法
TW201507097A (zh) 半導體晶片及具有半導體晶片之半導體裝置
JP2006245076A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150715

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150715

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160510

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160623

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160809

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160819

R150 Certificate of patent or registration of utility model

Ref document number: 5993248

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150