JP5955323B2 - 構成可能な電力状態をもつダイナミックｒａｍｐｈｙインタフェース - Google Patents

構成可能な電力状態をもつダイナミックｒａｍｐｈｙインタフェース Download PDF

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JP5955323B2
JP5955323B2 JP2013529258A JP2013529258A JP5955323B2 JP 5955323 B2 JP5955323 B2 JP 5955323B2 JP 2013529258 A JP2013529258 A JP 2013529258A JP 2013529258 A JP2013529258 A JP 2013529258A JP 5955323 B2 JP5955323 B2 JP 5955323B2
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power
interface
context
contexts
memory
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JP2013543612A (ja
JP2013543612A5 (enExample
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サールズ ショーン
サールズ ショーン
ティー． ハンフリーズ ニコラス
ティー． ハンフリーズ ニコラス
ダブリュ． アミック ブライアン
ダブリュ． アミック ブライアン
ダブリュ． リーブス リチャード
ダブリュ． リーブス リチャード
チョウ ハンウー
チョウ ハンウー
エル． ペティジョン ロナルド
エル． ペティジョン ロナルド
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
JP2013529258A 2010-09-13 2011-09-13 構成可能な電力状態をもつダイナミックｒａｍｐｈｙインタフェース Active JP5955323B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38208910P 2010-09-13 2010-09-13
US61/382,089 2010-09-13
US12/910,412 2010-10-22
US12/910,412 US8356155B2 (en) 2010-09-13 2010-10-22 Dynamic RAM Phy interface with configurable power states
PCT/US2011/051345 WO2012037086A1 (en) 2010-09-13 2011-09-13 Dynamic ram phy interface with configurable power states

Publications (3)

Publication Number Publication Date
JP2013543612A JP2013543612A (ja) 2013-12-05
JP2013543612A5 JP2013543612A5 (enExample) 2016-02-12
JP5955323B2 true JP5955323B2 (ja) 2016-07-20

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JP2013529258A Active JP5955323B2 (ja) 2010-09-13 2011-09-13 構成可能な電力状態をもつダイナミックｒａｍｐｈｙインタフェース

Country Status (6)

Country Link
US (2) US8356155B2 (enExample)
EP (1) EP2616946B1 (enExample)
JP (1) JP5955323B2 (enExample)
KR (1) KR101879707B1 (enExample)
CN (1) CN103168296B (enExample)
WO (1) WO2012037086A1 (enExample)

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US10275386B2 (en) 2014-06-27 2019-04-30 Advanced Micro Devices, Inc. Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays
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US9733957B2 (en) * 2014-09-05 2017-08-15 Qualcomm Incorporated Frequency and power management
CN104536917B (zh) * 2015-01-19 2017-04-26 中国电子科技集团公司第二十四研究所 应用于fpaa的基于存储器的多功能动态配置电路
US10409357B1 (en) * 2016-09-30 2019-09-10 Cadence Design Systems, Inc. Command-oriented low power control method of high-bandwidth-memory system
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KR102340446B1 (ko) * 2017-09-08 2021-12-21 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
CN110347620A (zh) * 2019-05-29 2019-10-18 深圳市紫光同创电子有限公司 一种fpga电路和系统
US20210200298A1 (en) * 2019-12-30 2021-07-01 Advanced Micro Devices, Inc. Long-idle state system and method
US11176986B2 (en) * 2019-12-30 2021-11-16 Advanced Micro Devices, Inc. Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
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US11609879B2 (en) * 2021-02-26 2023-03-21 Nvidia Corporation Techniques for configuring parallel processors for different application domains
US12437827B2 (en) * 2021-12-29 2025-10-07 Advanced Micro Devices, Inc. DRAM specific interface calibration via programmable training sequences
US12079490B2 (en) * 2021-12-29 2024-09-03 Advanced Micro Devices, Inc. Reducing power consumption associated with frequency transitioning in a memory interface
CN114492286B (zh) * 2022-01-18 2025-02-14 Oppo广东移动通信有限公司 控制芯片的方法及装置
CN115344215B (zh) * 2022-08-29 2025-03-18 深圳市紫光同创电子股份有限公司 存储器训练方法及系统
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Publication number Publication date
CN103168296A (zh) 2013-06-19
WO2012037086A1 (en) 2012-03-22
JP2013543612A (ja) 2013-12-05
US9274938B2 (en) 2016-03-01
KR101879707B1 (ko) 2018-07-18
US8356155B2 (en) 2013-01-15
US20120066445A1 (en) 2012-03-15
US20130124806A1 (en) 2013-05-16
EP2616946B1 (en) 2014-06-04
KR20140007331A (ko) 2014-01-17
EP2616946A1 (en) 2013-07-24
CN103168296B (zh) 2016-08-03

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