CN103168296B - 带有可配置功率状态的动态ram phy接口 - Google Patents

带有可配置功率状态的动态ram phy接口 Download PDF

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Publication number
CN103168296B
CN103168296B CN201180049362.4A CN201180049362A CN103168296B CN 103168296 B CN103168296 B CN 103168296B CN 201180049362 A CN201180049362 A CN 201180049362A CN 103168296 B CN103168296 B CN 103168296B
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power context
power
context
physical store
interface
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Chinese (zh)
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CN103168296A (zh
Inventor
肖恩·瑟尔斯
尼古拉斯·T·汉弗莱斯
布莱恩·W·阿米克
理查德·W·里夫斯
赵汉宇
罗纳德·L·佩蒂约翰
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
CN201180049362.4A 2010-09-13 2011-09-13 带有可配置功率状态的动态ram phy接口 Active CN103168296B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38208910P 2010-09-13 2010-09-13
US61/382,089 2010-09-13
US12/910,412 2010-10-22
US12/910,412 US8356155B2 (en) 2010-09-13 2010-10-22 Dynamic RAM Phy interface with configurable power states
PCT/US2011/051345 WO2012037086A1 (en) 2010-09-13 2011-09-13 Dynamic ram phy interface with configurable power states

Publications (2)

Publication Number Publication Date
CN103168296A CN103168296A (zh) 2013-06-19
CN103168296B true CN103168296B (zh) 2016-08-03

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CN201180049362.4A Active CN103168296B (zh) 2010-09-13 2011-09-13 带有可配置功率状态的动态ram phy接口

Country Status (6)

Country Link
US (2) US8356155B2 (enExample)
EP (1) EP2616946B1 (enExample)
JP (1) JP5955323B2 (enExample)
KR (1) KR101879707B1 (enExample)
CN (1) CN103168296B (enExample)
WO (1) WO2012037086A1 (enExample)

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US10275386B2 (en) 2014-06-27 2019-04-30 Advanced Micro Devices, Inc. Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays
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CN104536917B (zh) * 2015-01-19 2017-04-26 中国电子科技集团公司第二十四研究所 应用于fpaa的基于存储器的多功能动态配置电路
US10409357B1 (en) * 2016-09-30 2019-09-10 Cadence Design Systems, Inc. Command-oriented low power control method of high-bandwidth-memory system
JP2018101835A (ja) * 2016-12-19 2018-06-28 株式会社東芝 携帯可能電子装置、及びｉｃカード
KR102340446B1 (ko) * 2017-09-08 2021-12-21 삼성전자주식회사 스토리지 장치 및 그것의 데이터 트레이닝 방법
CN110347620A (zh) * 2019-05-29 2019-10-18 深圳市紫光同创电子有限公司 一种fpga电路和系统
US11176986B2 (en) * 2019-12-30 2021-11-16 Advanced Micro Devices, Inc. Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
US20210200298A1 (en) * 2019-12-30 2021-07-01 Advanced Micro Devices, Inc. Long-idle state system and method
US11100028B1 (en) 2020-04-27 2021-08-24 Apex Semiconductor Programmable I/O switch/bridge chiplet
US12322433B2 (en) 2020-12-22 2025-06-03 Intel Corporation Power and performance optimization in a memory subsystem
US11609879B2 (en) * 2021-02-26 2023-03-21 Nvidia Corporation Techniques for configuring parallel processors for different application domains
US12437827B2 (en) * 2021-12-29 2025-10-07 Advanced Micro Devices, Inc. DRAM specific interface calibration via programmable training sequences
US12079490B2 (en) * 2021-12-29 2024-09-03 Advanced Micro Devices, Inc. Reducing power consumption associated with frequency transitioning in a memory interface
CN114492286B (zh) * 2022-01-18 2025-02-14 Oppo广东移动通信有限公司 控制芯片的方法及装置
CN115344215B (zh) * 2022-08-29 2025-03-18 深圳市紫光同创电子股份有限公司 存储器训练方法及系统
US12072381B2 (en) 2022-10-18 2024-08-27 Micron Technology, Inc. Multi-modal memory apparatuses and systems
US20240355379A1 (en) * 2023-04-21 2024-10-24 Advanced Micro Devices, Inc. Voltage Range for Training Physical Memory
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US20050198542A1 (en) * 2004-03-08 2005-09-08 David Freker Method and apparatus for a variable memory enable deassertion wait time
US20060083093A1 (en) * 2004-10-15 2006-04-20 Dover Lance W Non-volatile configuration data storage for a configurable memory
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CN1768330A (zh) * 2003-04-14 2006-05-03 国际商业机器公司 具有容错地址和命令总线的高可靠性存储器模块
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Also Published As

Publication number Publication date
WO2012037086A1 (en) 2012-03-22
CN103168296A (zh) 2013-06-19
KR20140007331A (ko) 2014-01-17
US20120066445A1 (en) 2012-03-15
JP5955323B2 (ja) 2016-07-20
EP2616946B1 (en) 2014-06-04
US8356155B2 (en) 2013-01-15
US9274938B2 (en) 2016-03-01
KR101879707B1 (ko) 2018-07-18
US20130124806A1 (en) 2013-05-16
JP2013543612A (ja) 2013-12-05
EP2616946A1 (en) 2013-07-24

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