JP2013543612A5 - - Google Patents
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- JP2013543612A5 JP2013543612A5 JP2013529258A JP2013529258A JP2013543612A5 JP 2013543612 A5 JP2013543612 A5 JP 2013543612A5 JP 2013529258 A JP2013529258 A JP 2013529258A JP 2013529258 A JP2013529258 A JP 2013529258A JP 2013543612 A5 JP2013543612 A5 JP 2013543612A5
- Authority
- JP
- Japan
- Prior art keywords
- power
- contexts
- interface
- memory interface
- physical memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 10
- 238000012508 change request Methods 0.000 claims 5
- 230000004044 response Effects 0.000 claims 5
- 238000001193 catalytic steam reforming Methods 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US38208910P | 2010-09-13 | 2010-09-13 | |
| US61/382,089 | 2010-09-13 | ||
| US12/910,412 US8356155B2 (en) | 2010-09-13 | 2010-10-22 | Dynamic RAM Phy interface with configurable power states |
| US12/910,412 | 2010-10-22 | ||
| PCT/US2011/051345 WO2012037086A1 (en) | 2010-09-13 | 2011-09-13 | Dynamic ram phy interface with configurable power states |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013543612A JP2013543612A (ja) | 2013-12-05 |
| JP2013543612A5 true JP2013543612A5 (enExample) | 2016-02-12 |
| JP5955323B2 JP5955323B2 (ja) | 2016-07-20 |
Family
ID=44674909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013529258A Active JP5955323B2 (ja) | 2010-09-13 | 2011-09-13 | 構成可能な電力状態をもつダイナミックramphyインタフェース |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US8356155B2 (enExample) |
| EP (1) | EP2616946B1 (enExample) |
| JP (1) | JP5955323B2 (enExample) |
| KR (1) | KR101879707B1 (enExample) |
| CN (1) | CN103168296B (enExample) |
| WO (1) | WO2012037086A1 (enExample) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8799553B2 (en) * | 2010-04-13 | 2014-08-05 | Apple Inc. | Memory controller mapping on-the-fly |
| US9363115B2 (en) * | 2012-07-02 | 2016-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for aligning data bits |
| JP6184064B2 (ja) * | 2012-07-19 | 2017-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | メモリサブシステム、コンピュータ・システム |
| TWI493566B (zh) * | 2012-10-15 | 2015-07-21 | Via Tech Inc | 資料儲存裝置、儲存媒體控制器與控制方法 |
| US9305632B2 (en) | 2013-04-29 | 2016-04-05 | Qualcomm Incorporated | Frequency power manager |
| US9123408B2 (en) | 2013-05-24 | 2015-09-01 | Qualcomm Incorporated | Low latency synchronization scheme for mesochronous DDR system |
| EP3361391B1 (en) | 2013-12-26 | 2021-01-27 | INTEL Corporation | Multichip package link |
| US10275386B2 (en) | 2014-06-27 | 2019-04-30 | Advanced Micro Devices, Inc. | Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays |
| US9639495B2 (en) * | 2014-06-27 | 2017-05-02 | Advanced Micro Devices, Inc. | Integrated controller for training memory physical layer interface |
| KR20160029392A (ko) | 2014-09-05 | 2016-03-15 | 에스케이하이닉스 주식회사 | 임피던스 조정 회로 및 이를 이용한 반도체 메모리와 메모리 시스템 |
| US9733957B2 (en) * | 2014-09-05 | 2017-08-15 | Qualcomm Incorporated | Frequency and power management |
| CN104536917B (zh) * | 2015-01-19 | 2017-04-26 | 中国电子科技集团公司第二十四研究所 | 应用于fpaa的基于存储器的多功能动态配置电路 |
| US10409357B1 (en) * | 2016-09-30 | 2019-09-10 | Cadence Design Systems, Inc. | Command-oriented low power control method of high-bandwidth-memory system |
| JP2018101835A (ja) * | 2016-12-19 | 2018-06-28 | 株式会社東芝 | 携帯可能電子装置、及びicカード |
| KR102340446B1 (ko) * | 2017-09-08 | 2021-12-21 | 삼성전자주식회사 | 스토리지 장치 및 그것의 데이터 트레이닝 방법 |
| CN110347620A (zh) * | 2019-05-29 | 2019-10-18 | 深圳市紫光同创电子有限公司 | 一种fpga电路和系统 |
| US20210200298A1 (en) * | 2019-12-30 | 2021-07-01 | Advanced Micro Devices, Inc. | Long-idle state system and method |
| US11176986B2 (en) * | 2019-12-30 | 2021-11-16 | Advanced Micro Devices, Inc. | Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training |
| US11100028B1 (en) | 2020-04-27 | 2021-08-24 | Apex Semiconductor | Programmable I/O switch/bridge chiplet |
| US12322433B2 (en) | 2020-12-22 | 2025-06-03 | Intel Corporation | Power and performance optimization in a memory subsystem |
| US11609879B2 (en) * | 2021-02-26 | 2023-03-21 | Nvidia Corporation | Techniques for configuring parallel processors for different application domains |
| US12079490B2 (en) * | 2021-12-29 | 2024-09-03 | Advanced Micro Devices, Inc. | Reducing power consumption associated with frequency transitioning in a memory interface |
| US12437827B2 (en) * | 2021-12-29 | 2025-10-07 | Advanced Micro Devices, Inc. | DRAM specific interface calibration via programmable training sequences |
| CN114492286B (zh) * | 2022-01-18 | 2025-02-14 | Oppo广东移动通信有限公司 | 控制芯片的方法及装置 |
| CN115344215B (zh) * | 2022-08-29 | 2025-03-18 | 深圳市紫光同创电子股份有限公司 | 存储器训练方法及系统 |
| US12072381B2 (en) * | 2022-10-18 | 2024-08-27 | Micron Technology, Inc. | Multi-modal memory apparatuses and systems |
| US20240355379A1 (en) * | 2023-04-21 | 2024-10-24 | Advanced Micro Devices, Inc. | Voltage Range for Training Physical Memory |
| US20250037750A1 (en) * | 2023-07-26 | 2025-01-30 | Advanced Micro Devices, Inc. | Memory self-refresh power gating |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4631659A (en) * | 1984-03-08 | 1986-12-23 | Texas Instruments Incorporated | Memory interface with automatic delay state |
| US6154821A (en) * | 1998-03-10 | 2000-11-28 | Rambus Inc. | Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain |
| US6401213B1 (en) * | 1999-07-09 | 2002-06-04 | Micron Technology, Inc. | Timing circuit for high speed memory |
| JP5034133B2 (ja) * | 2000-02-29 | 2012-09-26 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
| ATE514989T1 (de) * | 2000-09-26 | 2011-07-15 | Oracle America Inc | Verfahren und system zur steuerung temperaturzyklen |
| US6618791B1 (en) * | 2000-09-29 | 2003-09-09 | Intel Corporation | System and method for controlling power states of a memory device via detection of a chip select signal |
| US6788593B2 (en) * | 2001-02-28 | 2004-09-07 | Rambus, Inc. | Asynchronous, high-bandwidth memory component using calibrated timing elements |
| KR100403347B1 (ko) * | 2001-09-14 | 2003-11-01 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 파워-업 발생회로 |
| US7000065B2 (en) * | 2002-01-02 | 2006-02-14 | Intel Corporation | Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers |
| US6816994B2 (en) * | 2002-06-21 | 2004-11-09 | Micron Technology, Inc. | Low power buffer implementation |
| US7234099B2 (en) * | 2003-04-14 | 2007-06-19 | International Business Machines Corporation | High reliability memory module with a fault tolerant address and command bus |
| US6876593B2 (en) * | 2003-07-01 | 2005-04-05 | Intel Corporation | Method and apparatus for partial refreshing of DRAMS |
| US20050198542A1 (en) | 2004-03-08 | 2005-09-08 | David Freker | Method and apparatus for a variable memory enable deassertion wait time |
| US7386654B2 (en) | 2004-10-15 | 2008-06-10 | Intel Corporation | Non-volatile configuration data storage for a configurable memory |
| KR100673904B1 (ko) * | 2005-04-30 | 2007-01-25 | 주식회사 하이닉스반도체 | 반도체메모리소자 |
| US7471130B2 (en) * | 2005-05-19 | 2008-12-30 | Micron Technology, Inc. | Graduated delay line for increased clock skew correction circuit operating range |
| US8244971B2 (en) * | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
| JP4615461B2 (ja) * | 2006-03-10 | 2011-01-19 | 京セラミタ株式会社 | メモリコントローラ |
| JP2007249738A (ja) * | 2006-03-17 | 2007-09-27 | Kawasaki Microelectronics Kk | メモリアクセス制御装置 |
| US7869287B2 (en) | 2008-03-31 | 2011-01-11 | Advanced Micro Devices, Inc. | Circuit for locking a delay locked loop (DLL) and method therefor |
| JP2010160724A (ja) * | 2009-01-09 | 2010-07-22 | Ricoh Co Ltd | メモリ制御システム、メモリ制御方法、メモリ制御プログラム及び記録媒体 |
-
2010
- 2010-10-22 US US12/910,412 patent/US8356155B2/en active Active
-
2011
- 2011-09-13 KR KR1020137009085A patent/KR101879707B1/ko active Active
- 2011-09-13 CN CN201180049362.4A patent/CN103168296B/zh active Active
- 2011-09-13 WO PCT/US2011/051345 patent/WO2012037086A1/en not_active Ceased
- 2011-09-13 JP JP2013529258A patent/JP5955323B2/ja active Active
- 2011-09-13 EP EP11760647.5A patent/EP2616946B1/en active Active
-
2013
- 2013-01-09 US US13/737,306 patent/US9274938B2/en active Active
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