JP5944589B2 - セル内に複数の磁気トンネル接合デバイスを備えたｏｔｐスキーム - Google Patents

セル内に複数の磁気トンネル接合デバイスを備えたｏｔｐスキーム Download PDF

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JP5944589B2
JP5944589B2 JP2015532107A JP2015532107A JP5944589B2 JP 5944589 B2 JP5944589 B2 JP 5944589B2 JP 2015532107 A JP2015532107 A JP 2015532107A JP 2015532107 A JP2015532107 A JP 2015532107A JP 5944589 B2 JP5944589 B2 JP 5944589B2
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Prior art keywords
tunnel junction
magnetic tunnel
sense amplifier
unit cell
coupled
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Japanese (ja)
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JP2015534204A (ja
JP2015534204A5 (enExample
Inventor
ジュン・ピル・キム
テヒュン・キム
スンリュル・キム
カンホ・イ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/02—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using magnetic or inductive elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/146—Write once memory, i.e. allowing changing of memory content by writing additional bits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/78—Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2015532107A 2012-09-13 2013-09-13 セル内に複数の磁気トンネル接合デバイスを備えたｏｔｐスキーム Expired - Fee Related JP5944589B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/613,125 2012-09-13
US13/613,125 US9165631B2 (en) 2012-09-13 2012-09-13 OTP scheme with multiple magnetic tunnel junction devices in a cell
PCT/US2013/059809 WO2014043575A1 (en) 2012-09-13 2013-09-13 Otp scheme with multiple magnetic tunnel junction devices in a cell

Publications (3)

Publication Number Publication Date
JP2015534204A JP2015534204A (ja) 2015-11-26
JP2015534204A5 JP2015534204A5 (enExample) 2016-01-28
JP5944589B2 true JP5944589B2 (ja) 2016-07-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015532107A Expired - Fee Related JP5944589B2 (ja) 2012-09-13 2013-09-13 セル内に複数の磁気トンネル接合デバイスを備えたｏｔｐスキーム

Country Status (4)

Country Link
US (1) US9165631B2 (enExample)
JP (1) JP5944589B2 (enExample)
CN (1) CN104620319B (enExample)
WO (1) WO2014043575A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
US9524765B2 (en) * 2014-08-15 2016-12-20 Qualcomm Incorporated Differential magnetic tunnel junction pair including a sense layer with a high coercivity portion
US9489999B2 (en) 2014-11-26 2016-11-08 Qualcomm Incorporated Magnetic tunnel junction resistance comparison based physical unclonable function
US9529660B2 (en) 2015-03-03 2016-12-27 Intel Corporation Apparatus and method for detecting single flip-error in a complementary resistive memory
US9373395B1 (en) * 2015-03-04 2016-06-21 Intel Corporation Apparatus to reduce retention failure in complementary resistive memory
US9805816B2 (en) * 2015-04-03 2017-10-31 Headway Technologies, Inc. Implementation of a one time programmable memory using a MRAM stack design
CN104835530B (zh) * 2015-06-05 2018-08-03 武汉新芯集成电路制造有限公司 一种电子熔丝结构电路
US9852805B2 (en) * 2015-06-25 2017-12-26 Kilopass Technology, Inc. Write enhancement for one time programmable (OTP) semiconductors
US10181357B2 (en) * 2015-08-18 2019-01-15 Ememory Technology Inc. Code generating apparatus and one time programming block
US9715916B1 (en) * 2016-03-24 2017-07-25 Intel Corporation Supply-switched dual cell memory bitcell
CN106128496A (zh) * 2016-06-16 2016-11-16 中电海康集团有限公司 一种基于电容机构的一次性可编程器件及编程实现方法
CN106128497A (zh) * 2016-06-16 2016-11-16 中电海康集团有限公司 一种带有读出电路的一次性可编程器件及数据读取方法
CN106128495A (zh) * 2016-06-16 2016-11-16 中电海康集团有限公司 一种一次性可编程器件及编程实现方法
CN107767906A (zh) * 2016-08-23 2018-03-06 中电海康集团有限公司 一种磁性随机存储器
KR102496506B1 (ko) 2016-10-14 2023-02-06 삼성전자주식회사 복수의 퓨즈 비트들을 독출하는 오티피 메모리 장치
US9922723B1 (en) 2017-01-17 2018-03-20 Nxp Usa, Inc. Volatile latch circuit with tamper resistant non-volatile latch backup
JP2018148159A (ja) 2017-03-09 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 磁気メモリ、磁気メモリの記録方法及び磁気メモリの読み出し方法
US10855287B2 (en) 2018-02-20 2020-12-01 United States Of America, As Represented By The Secretary Of The Navy Non-volatile multiple time programmable integrated circuit system with selective conversion to one time programmable or permanent configuration bit programming capabilities and related methods
US11133044B2 (en) * 2018-06-01 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interleaved routing for MRAM cell selection
US10878928B2 (en) * 2018-09-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. One-time-programmable (OTP) implementation using magnetic junctions
US10699764B1 (en) * 2018-12-14 2020-06-30 Nxp Usa, Inc. MRAM memory with OTP cells
JP2020155727A (ja) 2019-03-22 2020-09-24 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びこれを備えた電子機器
US11264991B2 (en) 2019-11-26 2022-03-01 The Trustees Of Indiana University Field-programmable gate array with updatable security schemes
US10861524B1 (en) * 2019-12-11 2020-12-08 Nxp Usa, Inc. Magnetoresistive random access memory (MRAM) with OTP cells
US11049539B1 (en) 2020-04-29 2021-06-29 Nxp Usa, Inc. Magnetoresistive random access memory (MRAM) with OTP cells
US12035540B2 (en) 2020-07-23 2024-07-09 Samsung Electronics Co., Ltd. Magnetic memory device
US12424293B2 (en) 2023-03-23 2025-09-23 SanDisk Technologies, Inc. One-time programmable memory devices and methods

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473336B2 (en) * 1999-12-16 2002-10-29 Kabushiki Kaisha Toshiba Magnetic memory device
JP3800925B2 (ja) * 2000-05-15 2006-07-26 日本電気株式会社 磁気ランダムアクセスメモリ回路
US6324093B1 (en) * 2000-09-15 2001-11-27 Hewlett-Packard Company Write-once thin-film memory
DE60205569T2 (de) * 2001-12-21 2006-05-18 Kabushiki Kaisha Toshiba MRAM mit gestapelten Speicherzellen
US6590797B1 (en) 2002-01-09 2003-07-08 Tower Semiconductor Ltd. Multi-bit programmable memory cell having multiple anti-fuse elements
JP4355136B2 (ja) * 2002-12-05 2009-10-28 シャープ株式会社 不揮発性半導体記憶装置及びその読み出し方法
JP2004199833A (ja) * 2002-12-20 2004-07-15 Fujitsu Ltd 不揮発性半導体記憶装置の制御方法及び不揮発性半導体記憶装置
JP3766380B2 (ja) 2002-12-25 2006-04-12 株式会社東芝 磁気ランダムアクセスメモリ及びその磁気ランダムアクセスメモリのデータ読み出し方法
TW200527656A (en) * 2004-02-05 2005-08-16 Renesas Tech Corp Semiconductor device
JP4478980B2 (ja) * 2004-10-05 2010-06-09 エルピーダメモリ株式会社 ヒューズ回路及びそれを利用した半導体装置
US7254078B1 (en) 2006-02-22 2007-08-07 International Business Machines Corporation System and method for increasing reliability of electrical fuse programming
US7567449B2 (en) 2006-10-27 2009-07-28 Xilinx, Inc. One-time-programmable logic bit with multiple logic elements
US7688613B2 (en) 2007-04-14 2010-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for controlling multiple electrical fuses with one program device
TWI415124B (zh) 2007-08-09 2013-11-11 Ind Tech Res Inst 磁性隨機存取記憶體
US7577020B2 (en) 2007-10-01 2009-08-18 Shine Chung System and method for reading multiple magnetic tunnel junctions with a single select transistor
US7933136B2 (en) 2008-11-07 2011-04-26 Seagate Technology Llc Non-volatile memory cell with multiple resistive sense elements sharing a common switching device
JP2010225259A (ja) * 2009-02-27 2010-10-07 Renesas Electronics Corp 半導体装置
US8363460B2 (en) 2010-04-07 2013-01-29 Avalanche Technology, Inc. Method and apparatus for programming a magnetic tunnel junction (MTJ)
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
US20120134200A1 (en) 2010-11-29 2012-05-31 Seagate Technology Llc Magnetic Memory Cell With Multi-Level Cell (MLC) Data Storage Capability

Also Published As

Publication number Publication date
CN104620319A (zh) 2015-05-13
US9165631B2 (en) 2015-10-20
WO2014043575A1 (en) 2014-03-20
CN104620319B (zh) 2017-11-14
JP2015534204A (ja) 2015-11-26
US20140071740A1 (en) 2014-03-13

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