JP5940711B2 - スタンダードセルのアーキテクチャと関連付けられるデバイスの製造方法 - Google Patents
スタンダードセルのアーキテクチャと関連付けられるデバイスの製造方法 Download PDFInfo
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- JP5940711B2 JP5940711B2 JP2015101927A JP2015101927A JP5940711B2 JP 5940711 B2 JP5940711 B2 JP 5940711B2 JP 2015101927 A JP2015101927 A JP 2015101927A JP 2015101927 A JP2015101927 A JP 2015101927A JP 5940711 B2 JP5940711 B2 JP 5940711B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 20
- 230000008569 process Effects 0.000 description 17
- 238000000059 patterning Methods 0.000 description 15
- 238000013461 design Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000011960 computer-aided design Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000002898 library design Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
102 第1のアクティブ領域
104 第2のアクティブ領域
106 ポリラインの第1のセット
108 ポリラインの第2のセット
202 第1のアクティブ領域
204 第2のアクティブ領域
206 ポリライン
208 ポリライン
210 ポリライン
212 第1のマスク
214 第2のマスク
Claims (9)
- 互いに離隔される第1のアクティブ領域及び第2のアクティブ領域を提供するステップと、
前記第1のアクティブ領域及び前記第2のアクティブ領域にわたって複数のポリラインを提供するステップであって、前記複数のポリラインが、一定の間隔だけ離隔されるステップと、
第1マスクを用いて前記複数のポリラインをパターニングして前記第1のアクティブ領域に形成される第1のセットのポリライン及び前記第2のアクティブ領域に形成される第2のセットのポリラインを形成するステップであって、前記第1のセットのポリラインの幅が前記第1のアクティブ領域の第1のチャネル長に対応し、前記第2のセットのポリラインの幅が前記第2のアクティブ領域の第2のチャネル長に対応するステップと、
第2マスクを用いて前記複数のポリラインを前記第1のセットのポリラインと前記第2のセットのポリラインに分割するステップと、
含む、スタンダードセルのアーキテクチャと関連付けられるデバイスの製造方法。 - 前記第1のアクティブ領域及び前記第2のアクティブ領域が離隔される距離が、135nmである、請求項1に記載の製造方法。
- 前記第1のチャネル長が、20nmと30nmである、請求項1又は2に記載の製造方法。
- 前記第2のチャネル長が、30nmと40nmである、請求項1から3の何れか一項に記載の製造方法。
- セルの間隔が140nmである、請求項1から4の何れか一項に記載の製造方法。
- 前記第1のセットのポリラインの各々の中心が、前記第2のセットのポリラインの各々の中心に揃うように配置される、請求項1から5の何れか一項に記載の製造方法。
- 前記第1のセットのポリラインの端と前記第1のアクティブ領域の端との間の距離が、31.5nmである、請求項1から6の何れか一項に記載の製造方法。
- 前記第2のセットのポリラインの端と前記第2のアクティブ領域の端との間の距離が、31.5nmである、請求項1から7の何れか一項に記載の製造方法。
- 前記第1のセットのポリラインの両端が、互いに揃えられる、請求項1から8の何れか一項に記載の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/004,460 | 2011-01-11 | ||
US13/004,460 US8610176B2 (en) | 2011-01-11 | 2011-01-11 | Standard cell architecture using double poly patterning for multi VT devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013549527A Division JP6037570B2 (ja) | 2011-01-11 | 2012-01-11 | 複数の電圧閾値を有するデバイスのための二重のポリラインパターニングを用いたスタンダードセルのアーキテクチャ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015156517A JP2015156517A (ja) | 2015-08-27 |
JP5940711B2 true JP5940711B2 (ja) | 2016-06-29 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013549527A Expired - Fee Related JP6037570B2 (ja) | 2011-01-11 | 2012-01-11 | 複数の電圧閾値を有するデバイスのための二重のポリラインパターニングを用いたスタンダードセルのアーキテクチャ |
JP2015101927A Expired - Fee Related JP5940711B2 (ja) | 2011-01-11 | 2015-05-19 | スタンダードセルのアーキテクチャと関連付けられるデバイスの製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013549527A Expired - Fee Related JP6037570B2 (ja) | 2011-01-11 | 2012-01-11 | 複数の電圧閾値を有するデバイスのための二重のポリラインパターニングを用いたスタンダードセルのアーキテクチャ |
Country Status (7)
Country | Link |
---|---|
US (1) | US8610176B2 (ja) |
EP (1) | EP2664001B1 (ja) |
JP (2) | JP6037570B2 (ja) |
KR (1) | KR101538350B1 (ja) |
CN (1) | CN103299423B (ja) |
TW (1) | TW201250996A (ja) |
WO (1) | WO2012097101A1 (ja) |
Families Citing this family (11)
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US9263279B2 (en) | 2013-04-17 | 2016-02-16 | Qualcomm Incorporated | Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features |
US9076775B2 (en) | 2013-09-04 | 2015-07-07 | Qualcomm Incorporated | System and method of varying gate lengths of multiple cores |
US9691868B2 (en) * | 2013-11-22 | 2017-06-27 | Qualcomm Incorporated | Merging lithography processes for gate patterning |
US10141311B2 (en) | 2014-03-24 | 2018-11-27 | Intel Corporation | Techniques for achieving multiple transistor fin dimensions on a single die |
KR102245136B1 (ko) | 2015-02-24 | 2021-04-28 | 삼성전자 주식회사 | 반도체 소자 형성 방법 |
US9583493B2 (en) | 2015-04-08 | 2017-02-28 | Samsung Electronics Co., Ltd. | Integrated circuit and semiconductor device |
TWI695283B (zh) * | 2015-08-05 | 2020-06-01 | 聯華電子股份有限公司 | 半導體佈局結構及其設計方法 |
KR102342851B1 (ko) | 2015-08-17 | 2021-12-23 | 삼성전자주식회사 | 반도체 칩, 테스트 시스템 및 반도체 칩의 테스트 방법 |
US11569231B2 (en) | 2019-03-15 | 2023-01-31 | Intel Corporation | Non-planar transistors with channel regions having varying widths |
US20220093587A1 (en) * | 2020-09-18 | 2022-03-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit layout and method thereof |
KR20220046035A (ko) | 2020-10-06 | 2022-04-14 | 삼성전자주식회사 | 반도체 장치 |
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JP3777768B2 (ja) * | 1997-12-26 | 2006-05-24 | 株式会社日立製作所 | 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法 |
US6787469B2 (en) | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
US7100135B2 (en) | 2004-06-18 | 2006-08-29 | Intel Corporation | Method and system to evaluate signal line spacing |
US7340712B2 (en) | 2005-06-01 | 2008-03-04 | International Business Machines Corporation | System and method for creating a standard cell library for reduced leakage and improved performance |
JP2007096099A (ja) * | 2005-09-29 | 2007-04-12 | Toshiba Corp | 半導体装置の製造方法 |
US7469389B2 (en) | 2005-10-07 | 2008-12-23 | Kawasaki Microelectronics, Inc. | Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit |
US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
JP2007335512A (ja) * | 2006-06-13 | 2007-12-27 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
WO2008114341A1 (ja) * | 2007-03-16 | 2008-09-25 | Fujitsu Microelectronics Limited | 半導体装置およびその製造方法 |
JP2008235350A (ja) | 2007-03-16 | 2008-10-02 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
WO2008126270A1 (ja) * | 2007-03-30 | 2008-10-23 | Fujitsu Limited | 半導体集積回路 |
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JP5211689B2 (ja) | 2007-12-28 | 2013-06-12 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
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2011
- 2011-01-11 US US13/004,460 patent/US8610176B2/en not_active Expired - Fee Related
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2012
- 2012-01-11 TW TW101101134A patent/TW201250996A/zh unknown
- 2012-01-11 WO PCT/US2012/020993 patent/WO2012097101A1/en active Application Filing
- 2012-01-11 CN CN201280004896.XA patent/CN103299423B/zh not_active Expired - Fee Related
- 2012-01-11 EP EP12702653.2A patent/EP2664001B1/en not_active Not-in-force
- 2012-01-11 JP JP2013549527A patent/JP6037570B2/ja not_active Expired - Fee Related
- 2012-01-11 KR KR1020137020994A patent/KR101538350B1/ko active IP Right Grant
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2015
- 2015-05-19 JP JP2015101927A patent/JP5940711B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8610176B2 (en) | 2013-12-17 |
EP2664001A1 (en) | 2013-11-20 |
CN103299423A (zh) | 2013-09-11 |
JP6037570B2 (ja) | 2016-12-07 |
JP2014507067A (ja) | 2014-03-20 |
US20120180016A1 (en) | 2012-07-12 |
EP2664001B1 (en) | 2015-09-16 |
JP2015156517A (ja) | 2015-08-27 |
KR101538350B1 (ko) | 2015-07-22 |
TW201250996A (en) | 2012-12-16 |
WO2012097101A1 (en) | 2012-07-19 |
CN103299423B (zh) | 2016-08-24 |
KR20130114719A (ko) | 2013-10-17 |
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