JP5854440B2 - 低インピーダンス送信ライン - Google Patents

低インピーダンス送信ライン Download PDF

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Publication number
JP5854440B2
JP5854440B2 JP2013530313A JP2013530313A JP5854440B2 JP 5854440 B2 JP5854440 B2 JP 5854440B2 JP 2013530313 A JP2013530313 A JP 2013530313A JP 2013530313 A JP2013530313 A JP 2013530313A JP 5854440 B2 JP5854440 B2 JP 5854440B2
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JP
Japan
Prior art keywords
metallization layer
conductive vias
transmission line
portions
center tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013530313A
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English (en)
Japanese (ja)
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JP2013539301A (ja
JP2013539301A5 (https=
Inventor
ピー ギンスバーグ ブライアン
ピー ギンスバーグ ブライアン
ビー レンタラ ヴィジェイ
ビー レンタラ ヴィジェイ
エム ラマスワミ スリナス
エム ラマスワミ スリナス
エス ハルーン バヘル
エス ハルーン バヘル
ソク ウニョン
ソク ウニョン
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2013539301A publication Critical patent/JP2013539301A/ja
Publication of JP2013539301A5 publication Critical patent/JP2013539301A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Microwave Amplifiers (AREA)
JP2013530313A 2010-09-22 2011-09-22 低インピーダンス送信ライン Active JP5854440B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/888,208 2010-09-22
US12/888,208 US8476687B2 (en) 2010-09-22 2010-09-22 Low impedance transmisson line
PCT/US2011/052767 WO2012040468A2 (en) 2010-09-22 2011-09-22 Low impedance transmission line

Publications (3)

Publication Number Publication Date
JP2013539301A JP2013539301A (ja) 2013-10-17
JP2013539301A5 JP2013539301A5 (https=) 2014-10-16
JP5854440B2 true JP5854440B2 (ja) 2016-02-09

Family

ID=45816957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013530313A Active JP5854440B2 (ja) 2010-09-22 2011-09-22 低インピーダンス送信ライン

Country Status (4)

Country Link
US (1) US8476687B2 (https=)
JP (1) JP5854440B2 (https=)
CN (1) CN103098210B (https=)
WO (1) WO2012040468A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9166270B2 (en) 2012-11-21 2015-10-20 Texas Instruments Incorporated Balun with integrated decoupling as ground shield
CN103337682B (zh) * 2013-07-24 2015-03-25 东南大学 一种宽带、低损耗、高平衡度的片上巴伦
SG10201803274QA (en) * 2013-10-30 2018-06-28 Nestec Sa Machine and system for preparing a cooled food product with aerated or whipped texture in controlled manner
CN105938931A (zh) * 2016-02-29 2016-09-14 中国电力科学研究院 一种平衡不平衡转换器及其设计方法
CN105789803A (zh) * 2016-02-29 2016-07-20 中国电力科学研究院 一种平衡不平衡转换器及其设计方法
US10692967B1 (en) * 2018-12-04 2020-06-23 Analog Devices, Inc. High density self-routing metal-oxide-metal capacitor
CN115528024A (zh) * 2021-06-25 2022-12-27 瑞昱半导体股份有限公司 紧凑的电容结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281769A (en) 1990-11-05 1994-01-25 Nippon Telegraph And Telephone Corporation Dewall plating technique
JP2001111408A (ja) 1999-10-08 2001-04-20 Hitachi Ltd 高速信号伝送配線実装構造
US6714113B1 (en) * 2000-11-14 2004-03-30 International Business Machines Corporation Inductor for integrated circuits
JP2005027005A (ja) 2003-07-02 2005-01-27 Matsushita Electric Ind Co Ltd 高周波信号発生装置
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
EP1929285B1 (en) * 2005-09-30 2017-02-22 Silicon Laboratories Inc. An integrated electronic sensor and method for its production
JP4799992B2 (ja) 2005-10-18 2011-10-26 学校法人明星学苑 半導体装置及び半導体装置の特性調整方法
JP2007115357A (ja) * 2005-10-21 2007-05-10 Matsushita Electric Ind Co Ltd データ記録装置及びデータ記録方法
JP5103232B2 (ja) * 2008-03-18 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US20120068238A1 (en) 2012-03-22
JP2013539301A (ja) 2013-10-17
CN103098210A (zh) 2013-05-08
US8476687B2 (en) 2013-07-02
WO2012040468A2 (en) 2012-03-29
CN103098210B (zh) 2015-11-25
WO2012040468A3 (en) 2012-08-16

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