JP5851211B2 - 半導体パッケージ、半導体パッケージの製造方法及び半導体装置 - Google Patents

半導体パッケージ、半導体パッケージの製造方法及び半導体装置 Download PDF

Info

Publication number
JP5851211B2
JP5851211B2 JP2011247666A JP2011247666A JP5851211B2 JP 5851211 B2 JP5851211 B2 JP 5851211B2 JP 2011247666 A JP2011247666 A JP 2011247666A JP 2011247666 A JP2011247666 A JP 2011247666A JP 5851211 B2 JP5851211 B2 JP 5851211B2
Authority
JP
Japan
Prior art keywords
insulating layer
layer
semiconductor chip
interlayer insulating
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011247666A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013105840A (ja
JP2013105840A5 (https=
Inventor
清水　規良
規良 清水
六川　昭雄
昭雄 六川
井上　修
修 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011247666A priority Critical patent/JP5851211B2/ja
Priority to US13/667,504 priority patent/US8823187B2/en
Publication of JP2013105840A publication Critical patent/JP2013105840A/ja
Publication of JP2013105840A5 publication Critical patent/JP2013105840A5/ja
Application granted granted Critical
Publication of JP5851211B2 publication Critical patent/JP5851211B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H05K1/186—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2011247666A 2011-11-11 2011-11-11 半導体パッケージ、半導体パッケージの製造方法及び半導体装置 Active JP5851211B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011247666A JP5851211B2 (ja) 2011-11-11 2011-11-11 半導体パッケージ、半導体パッケージの製造方法及び半導体装置
US13/667,504 US8823187B2 (en) 2011-11-11 2012-11-02 Semiconductor package, semiconductor package manufacturing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011247666A JP5851211B2 (ja) 2011-11-11 2011-11-11 半導体パッケージ、半導体パッケージの製造方法及び半導体装置

Publications (3)

Publication Number Publication Date
JP2013105840A JP2013105840A (ja) 2013-05-30
JP2013105840A5 JP2013105840A5 (https=) 2014-09-04
JP5851211B2 true JP5851211B2 (ja) 2016-02-03

Family

ID=48279826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011247666A Active JP5851211B2 (ja) 2011-11-11 2011-11-11 半導体パッケージ、半導体パッケージの製造方法及び半導体装置

Country Status (2)

Country Link
US (1) US8823187B2 (https=)
JP (1) JP5851211B2 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
GB201301188D0 (en) 2013-01-23 2013-03-06 Cryogatt Systems Ltd RFID tag
JP2015072983A (ja) * 2013-10-02 2015-04-16 イビデン株式会社 プリント配線板、プリント配線板の製造方法、パッケージ−オン−パッケージ
JPWO2015076121A1 (ja) * 2013-11-20 2017-03-16 株式会社村田製作所 多層配線基板およびこれを備えるプローブカード
US9209154B2 (en) 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9679841B2 (en) * 2014-05-13 2017-06-13 Qualcomm Incorporated Substrate and method of forming the same
EP3195355B1 (en) 2014-09-19 2020-11-25 Intel Corporation Semiconductor packages with embedded bridge interconnects
US9756738B2 (en) * 2014-11-14 2017-09-05 Dyi-chung Hu Redistribution film for IC package
JP6373219B2 (ja) * 2015-03-31 2018-08-15 太陽誘電株式会社 部品内蔵基板および半導体モジュール
KR102450599B1 (ko) * 2016-01-12 2022-10-07 삼성전기주식회사 패키지기판
US11024757B2 (en) * 2016-01-15 2021-06-01 Sony Corporation Semiconductor device and imaging apparatus
US10276467B2 (en) * 2016-03-25 2019-04-30 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
JP6291094B2 (ja) * 2017-01-24 2018-03-14 信越化学工業株式会社 積層型半導体装置、及び封止後積層型半導体装置
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same
MX2021003898A (es) 2018-10-05 2021-06-04 Tmrw Life Sciences Inc Aparato para conservar e identificar muestras biológicas en condiciones criogénicas.
US20220157865A1 (en) * 2019-03-13 2022-05-19 Sony Semiconductor Solutions Corporation Semiconductor apparatus, imaging apparatus, and method of producing a semiconductor apparatus
JP7371882B2 (ja) * 2019-04-12 2023-10-31 株式会社ライジングテクノロジーズ 電子回路装置および電子回路装置の製造方法
WO2020250795A1 (ja) 2019-06-10 2020-12-17 株式会社ライジングテクノロジーズ 電子回路装置
US11139179B2 (en) * 2019-09-09 2021-10-05 Advanced Semiconductor Engineering, Inc. Embedded component package structure and manufacturing method thereof
MX2022005127A (es) 2019-10-29 2022-08-04 Tmrw Life Sciences Inc Aparato para facilitar la transferencia de especimenes biologicos almacenados en condiciones criogenicas.
CN113140520B (zh) * 2020-01-19 2024-11-08 江苏长电科技股份有限公司 封装结构及其成型方法
JP7014244B2 (ja) * 2020-03-03 2022-02-01 大日本印刷株式会社 インターポーザ基板
US11817187B2 (en) 2020-05-18 2023-11-14 TMRW Life Sciences, Inc. Handling and tracking of biological specimens for cryogenic storage
USD951481S1 (en) 2020-09-01 2022-05-10 TMRW Life Sciences, Inc. Cryogenic vial
JP7610303B2 (ja) 2020-09-24 2025-01-08 ティーエムアールダブリュ ライフサイエンシーズ，インコーポレイテツド 極低温条件で保管された生物学的試料の移送を容易にするためのワークステーション及び装置
JP7545768B2 (ja) 2020-10-02 2024-09-05 ティーエムアールダブリュ ライフサイエンシーズ，インコーポレイテツド 無線トランスポンダタグ付き試料容器及び／又はキャリアのための位置合わせ機構を有する問い合わせ装置及び／又はシステム
USD963194S1 (en) 2020-12-09 2022-09-06 TMRW Life Sciences, Inc. Cryogenic vial carrier
EP4259333B1 (en) 2020-12-10 2026-03-04 TMRW Life Sciences, Inc. Specimen holder with wireless transponder
US12125816B2 (en) * 2020-12-30 2024-10-22 Micron Technology, Inc. Semiconductor device assemblies and systems with one or more dies at least partially embedded in a redistribution layer (RDL) and methods for making the same
EP4252009B1 (en) 2021-01-13 2025-03-05 TMRW Life Sciences, Inc. System to pick and/or place specimen containers
CN112820694B (zh) * 2021-01-15 2022-05-27 上海航天电子通讯设备研究所 一种芯片屏蔽与气密封装方法和封装结构
US12527318B2 (en) 2021-10-08 2026-01-20 TMRW Life Sciences, Inc. Systems, apparatus and methods to pick and/or place specimen containers

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004146656A (ja) * 2002-10-25 2004-05-20 Denso Corp 多層配線基板及びその製造方法
JP2004228393A (ja) * 2003-01-24 2004-08-12 Seiko Epson Corp インターポーザ基板、半導体装置、半導体モジュール、電子機器および半導体モジュールの製造方法
JP4935163B2 (ja) * 2006-04-11 2012-05-23 日本電気株式会社 半導体チップ搭載用基板
JP5295596B2 (ja) * 2008-03-19 2013-09-18 新光電気工業株式会社 多層配線基板およびその製造方法
JP4489821B2 (ja) * 2008-07-02 2010-06-23 新光電気工業株式会社 半導体装置及びその製造方法
JP2010050150A (ja) * 2008-08-19 2010-03-04 Panasonic Corp 半導体装置及び半導体モジュール
JP5581519B2 (ja) * 2009-12-04 2014-09-03 新光電気工業株式会社 半導体パッケージとその製造方法
WO2011114766A1 (ja) * 2010-03-16 2011-09-22 日本電気株式会社 機能素子内蔵基板
JP5570855B2 (ja) * 2010-03-18 2014-08-13 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置及びその製造方法
JP5830843B2 (ja) * 2010-03-24 2015-12-09 富士通セミコンダクター株式会社 半導体ウエハとその製造方法、及び半導体チップ
WO2011125380A1 (ja) * 2010-04-08 2011-10-13 日本電気株式会社 半導体素子内蔵配線基板

Also Published As

Publication number Publication date
US20130119562A1 (en) 2013-05-16
JP2013105840A (ja) 2013-05-30
US8823187B2 (en) 2014-09-02

Similar Documents

Publication Publication Date Title
JP5851211B2 (ja) 半導体パッケージ、半導体パッケージの製造方法及び半導体装置
JP5977051B2 (ja) 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
JP6152254B2 (ja) 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
JP5566161B2 (ja) 回路パターンの浮き上がり現象を抑制するパッケージオンパッケージ及びその製造方法
JP6076653B2 (ja) 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP6375121B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6584939B2 (ja) 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法
JP4298559B2 (ja) 電子部品実装構造及びその製造方法
JP5795196B2 (ja) 半導体パッケージ
JP6352644B2 (ja) 配線基板及び半導体パッケージの製造方法
US9209146B2 (en) Electronic device packages having bumps and methods of manufacturing the same
JP4730426B2 (ja) 実装基板及び半導体モジュール
JP2012049219A (ja) 電子装置
KR20080088403A (ko) 배선 기판의 제조 방법, 반도체 장치의 제조 방법 및 배선기판
JP2015195263A (ja) 半導体装置及びその製造方法
JP2015106615A (ja) プリント配線板、プリント配線板の製造方法
CN112071821B (zh) 半导体封装基板及其制法与电子封装件
JP2017050313A (ja) プリント配線板及びプリント配線板の製造方法
TW201448139A (zh) 嵌埋式基板封裝構造及其製造方法
JP2017143096A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2017135286A (ja) 半導体装置及び半導体装置の製造方法
KR20250028573A (ko) 댐과 다층 구조의 언더필막을 포함하는 반도체 패키지
US20250379131A1 (en) Package substrate including fiber-reinforced dielectric layer, package structure including the package substrate and method of forming the same
JP2017050312A (ja) プリント配線板及びプリント配線板の製造方法
KR101340349B1 (ko) 패키지 기판 및 이의 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140723

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140723

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150316

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150407

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150527

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20151124

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20151202

R150 Certificate of patent or registration of utility model

Ref document number: 5851211

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150