JP5830847B2 - 半導体装置の製造方法及び接合方法 - Google Patents
半導体装置の製造方法及び接合方法 Download PDFInfo
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- JP5830847B2 JP5830847B2 JP2010236433A JP2010236433A JP5830847B2 JP 5830847 B2 JP5830847 B2 JP 5830847B2 JP 2010236433 A JP2010236433 A JP 2010236433A JP 2010236433 A JP2010236433 A JP 2010236433A JP 5830847 B2 JP5830847 B2 JP 5830847B2
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Description
受け側部材に仮搭載された半導体素子を、前記半導体素子を取り囲む液体を介して加圧加熱し、
前記加熱加圧による静水圧により、前記半導体素子を前記受け側部材に対して押圧するとともに、前記半導体素子の接続端子を前記受け側部材に溶融接合する。
第1部材の接続部を第2部材上に仮搭載し、
前記第2部材上に仮搭載された前記第1部材を液体又はゲル状液体で取り囲み、
前記液体又は前記ゲル状液体を加熱加圧して前記第1部材に対する静水圧を発生させるとともに、前記第1部材の接続部を前記第2部材に対して溶融接合する。
(付記1)
受け側部材に仮搭載された半導体素子を、前記半導体素子を取り囲む液体又はゲル状液体を介して加圧加熱し、
前記加熱加圧による静水圧により、前記半導体素子を前記受け側部材に対して押圧するとともに、前記半導体素子の接続端子を前記受け側部材に溶融接合する、
ことを特徴とする半導体装置の製造方法。
(付記2)
前記半導体素子を前記受け側部材上の接続部に位置あわせして仮搭載し、
前記受け側部材上に仮搭載された半導体素子上に前記液体又はゲル状液体を供給し、
前記液体又はゲル状液体を加熱加圧して前記静水圧を生じさせる
ことを特徴とする付記1に記載の半導体装置の製造方法。
(付記3)
前記半導体素子の前記接続端子と、前記受け側部材の前記接続部の少なくとも一方に、前記液体又はゲル状液体の加熱加圧温度で溶融する材料を用いることを特徴とする付記2に記載の半導体装置の製造方法。
(付記4)
前記半導体素子を前記液体又は前記ゲル状液体で取り囲む工程の前に、前記半導体素子の前記接続端子が形成されている面に、Bステージ化されたアンダーフィル材を配置する工程をさらに含むことを特徴とする付記2に記載の半導体装置の製造方法。
(付記5)
前記アンダーフィル材として、前記液体又は前記ゲル状液体の加熱温度により粘度が低下する材料を選択することを特徴する付記4に記載の半導体装置の製造方法。
(付記6)前記接続端子を前記受け側部材に溶融接合した後に、前記液体又はゲル状液体を硬化させてパッケージ樹脂として用いる付記1〜5のいずれか1に記載の半導体装置の製造方法。
(付記7)
前記接続端子の溶融接合後に、前記ゲル状液体を除去することを特徴とする付記1〜5のいずれか1に記載の半導体装置の製造方法。
(付記8)
第1部材の接続部を第2部材上に仮搭載し、
前記第2部材上に仮搭載された前記第1部材を液体又はゲル状液体で取り囲み、
前記液体又は前記ゲル状液体を加熱加圧して前記第1部材に対する静水圧を発生させるとともに、前記第1部材の接続部を前記第2部材に対して溶融接合する
ことを特徴とする接合方法。
10、10A、10B、50A、50B、72、73、74、76 半導体素子
13 はんだ
15、15a、15b 接続端子
20、60 基板(受け側部材)
22 受け側電極
30 液体又はゲル状液体
40 枠
Claims (6)
- アンダーフィル材を間に挟んで受け側部材に仮搭載された半導体素子を、前記半導体素子を取り囲む液体又はゲル状液体を介して、前記半導体素子の接続端子と前記受け側部材の接続部の少なくとも一方の溶融温度以上の温度で加熱加圧し、
前記加熱加圧による静水圧により、前記半導体素子を前記受け側部材の前記接続部に対して押圧するとともに、前記液体又はゲル状液体からの加熱により前記アンダーフィル材を軟化させ、前記静水圧による均等加圧下で前記半導体素子の前記接続端子を前記受け側部材の前記接続部に対して溶融接合し、
前記溶融接合後の冷却により前記アンダーフィル材を硬化させる
ことを特徴とする半導体装置の製造方法。 - 前記半導体素子の前記接続端子を前記受け側部材上の前記接続部に位置あわせして仮搭載し、
前記受け側部材上に仮搭載された半導体素子上に前記液体又はゲル状液体を供給し、
前記液体又はゲル状液体を加熱加圧して前記静水圧を生じさせる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記半導体素子の前記接続端子と、前記受け側部材の前記接続部の少なくとも一方に、前記液体又はゲル状液体の加熱加圧温度で溶融するはんだ材料を用いることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体素子上に前記液体又は前記ゲル状液体を供給する前に、前記半導体素子の前記接続端子が形成されている面に、Bステージ化された前記アンダーフィル材を配置する工程をさらに含むことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記アンダーフィル材として、前記液体又は前記ゲル状液体の加熱温度により粘度が低下する材料を選択することを特徴する請求項4に記載の半導体装置の製造方法。
- アンダーフィル材を間に挟んで第1部材のはんだ接続部を第2部材上に仮搭載し、
前記第2部材上に仮搭載された前記第1部材を液体又はゲル状液体で取り囲み、
前記液体又は前記ゲル状液体を前記はんだ接続部の溶融温度以上の温度で加熱加圧して静水圧を発生させて前記第1部材を前記第2部材に対して押圧し、前記液体又は前記ゲル状液体からの加熱により前記アンダーフィル材を軟化させるとともに、前記第1部材の前記はんだ接続部を前記第2部材に対して溶融接合し、
前記溶融接合後の冷却により前記アンダーフィル材を硬化させる
ことを特徴とする接合方法。
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TWI600701B (zh) * | 2012-07-19 | 2017-10-01 | Nagase Chemtex Corp | A semiconductor sealing epoxy resin composition and a method of manufacturing the semiconductor device |
JP6126834B2 (ja) * | 2012-12-20 | 2017-05-10 | ナミックス株式会社 | 先供給型半導体封止用液状樹脂組成物および半導体装置 |
JP6172654B2 (ja) | 2013-03-14 | 2017-08-02 | アルファーデザイン株式会社 | 部品加圧装置及び部品加圧装置を用いた加熱システム |
JP2014179419A (ja) | 2013-03-14 | 2014-09-25 | Alpha- Design Kk | 電子部品の接合方法 |
CN110582840A (zh) * | 2017-04-21 | 2019-12-17 | 日立化成株式会社 | 半导体装置及其制造方法 |
US20210013099A1 (en) * | 2019-07-10 | 2021-01-14 | Facebook Technologies, Llc | Reducing the planarity variation in a display device |
CN111370339B (zh) * | 2020-03-20 | 2022-02-22 | 中国科学院半导体研究所 | 晶圆的室温等静压金属键合方法 |
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JPH0671026B2 (ja) * | 1987-03-25 | 1994-09-07 | 三菱電機株式会社 | 半導体実装方法 |
EP0460286A3 (en) * | 1990-06-06 | 1992-02-26 | Siemens Aktiengesellschaft | Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing |
JP3565092B2 (ja) * | 1999-06-16 | 2004-09-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP2001035881A (ja) * | 1999-07-19 | 2001-02-09 | Fujitsu General Ltd | フリップチップ実装構造 |
JP4024458B2 (ja) * | 2000-06-27 | 2007-12-19 | 株式会社東芝 | 半導体装置の実装方法および半導体装置実装体の製造方法 |
US7331502B2 (en) * | 2001-03-19 | 2008-02-19 | Sumitomo Bakelite Company, Ltd. | Method of manufacturing electronic part and electronic part obtained by the method |
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JP2003264205A (ja) * | 2002-03-08 | 2003-09-19 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP4780023B2 (ja) * | 2007-04-09 | 2011-09-28 | 日立化成工業株式会社 | マルチチップモジュールの実装方法 |
JP2011044530A (ja) * | 2009-08-20 | 2011-03-03 | Panasonic Corp | はんだ接合方法およびはんだ接合装置 |
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