JP4780023B2 - マルチチップモジュールの実装方法 - Google Patents
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
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- H01L2224/7511—High pressure chamber
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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Description
また、本発明は、[2]基板上に複数個のチップを実装する方法であって、基板上の電極形成面と電極間に潜在性硬化剤を含有する接着剤を介在させ、基板の電極とこれに相対峙するチップの電極を位置合わせした状態で接着剤中の導電粒子もしくは電極間の直接接触により電気的接続が得られるように前記硬化剤の活性温度以下で仮接続し、この状態で導通検査および/又はチップ周囲の余剰接着剤を除去する工程を行った後、吸排気孔が設けられた密閉容器内の静水圧下で硬化剤の活性温度以上で加熱することを特徴とする、チップ高さの異なる場合または基板の両面に実装する場合のマルチチップモジュールの実装方法に関する。
また、本発明は、[3]上記[1]または上記[2]のいずれかにおいて、密閉容器内の静水圧下で実装する基板が複数枚であることを特徴とするマルチチップモジュールの実装方法に関する。
また、本発明は、[4]上記[1]ないし上記[3]のいずれかにおいて、加熱加圧時に厚み保持材として接着剤中に導電粒子または絶縁粒子が添加された接着剤を用いるマルチチップモジュールの実装方法に関する。
また、本発明は、[5]上記[1]ないし[4]のいずれかにおいて、密閉容器に試料の出し入れ口が設けられていることを特徴とするマルチチップモジュールの実装方法に関する。
また、本発明は、[6]上記[1]ないし[5]のいずれかにおいて、基板の電極とこれに相対峙するチップの電極を位置合わせし、接着剤の粘着性によりチップを基板上に仮付けした状態で、接着剤中の導電粒子もしくは電極間の直接接触により電気的接続が得られるように硬化剤の活性温度以下で仮接続することを特徴とするマルチチップモジュールの実装方法に関する。
実施例1
(1)接着剤の作製
フェノキシ樹脂(PKHA、ユニオンカーバイド社製高分子量エポキシ樹脂)とマイクロカプセル型潜在性硬化剤を含有する液状エポキシ樹脂(ノバキュアHP−3942HP、旭化成製、エポキシ当量185)の比率を30/70とし、酢酸エチルの30重量%溶液を得た。この溶液に、粒径3±0.2μmのポリスチレン系粒子にNi/Auの厚さ0.2/0.02μmの金属被覆を形成した導電性粒子を2体積%添加し混合分散した。5mm×11mmで厚み0.8mmのガラスエポキシ基板(FR−4グレ−ド)上に、高さ18μmの銅の回路を有し、回路端部が後記するICチップのバンプピッチに対応した接続電極を有するガラスエポキシ基板の接続領域に、前記分散液をスクリ−ン印刷で塗布し、100℃で20分乾燥し、電極上の厚みが20μmの潜在性硬化剤を含有する接着剤層を得た。この接着層のDSCによる活性温度は120℃である。
前記の接着剤付き基板に、ICチップ3個(高さ0.3、0.55、1.0mm)を配置し、CCDカメラによる電極の位置合わせを行った。接着剤は室温でも若干の粘着性がある状態であり、室温で接着面に押しつけることで基板に簡単に保持でき、チップの仮付け基板を得た。チップの仮付け基板を、プレッシャ−クッカ試験機の圧力釜に入れて、120℃、20kgf/mm2、10分間空気圧で処理後に室温に冷却して取出した。
(3)評価
各チップの電極と基板電極は良好に接続が可能であった。接着剤はチップ近傍のみに存在しているので、基板表面に不要接着剤はほとんどなかった。本実施例では、高さの異なるICチップ3個を基板面に接続できた。
実施例1と同様であるが、チップの仮付け基板を得た後で電極間の電気的接続を検査する中間検査工程を設けた。まず、70℃、10kgf/mm2で、スプリング装置で加圧しながら各接続点の接続抵抗をマルチメータで測定検査したところ、1個のICチップが異常であった。そこで異常チップを剥離して新規チップで前記同様の接続を行ったところ良好であった。本実施例では接着剤の硬化反応が不十分な状態なので、チップの剥離や、その後のアセトンを用いた清浄化も極めて簡単であり、リペア作業が容易であった。また、チップの周囲の余剰接着剤も同様にアセトンで簡単に除去可能であった。以上の通電検査工程およびリペア工程の後で、実施例1と同様圧力釜に入れて処理した。ところ、良好な接続特性を示した。接着剤の硬化後であると、チップの剥離や、その後の溶剤による清浄化が極めて困難であるが、本実施例によれば、狭い基板状に多数のチップが存在する場合も、リペア作業が極めて容易であった。
実施例1と同様であるが、図3例示のような両面基板とした。各チップの電極と基板電極は良好に接続が可能であった。なお本実施例では圧力釜の処理の際、チップの仮付け基板の下側になる面は、耐熱性の粘着テ−プでチップを接着剤面に押しつけて補強し、基板からチップ剥離のないようにした。
実施例1と同様であるが、接着剤の種類を変えた。すなわち、導電粒子を未添加とした。この場合も各チップの電極と基板電極は良好に接続が可能であった。バンプとガラスエポキシ基板の回路端部が直接接触し、接着剤で固定されているためと見られる。
2 チップ
3 接着剤
4 電極A
5 電極B
6 密閉容器
7 吸排気孔
8 定盤
9 加圧型
Claims (6)
- 基板上に複数個のチップを実装する方法であって、基板上の電極形成面と電極間に潜在性硬化剤を含有する接着剤を介在させ、基板の電極とこれに相対峙するチップの電極を位置合わせした状態で接着剤中の導電粒子もしくは電極間の直接接触により電気的接続が得られるように前記硬化剤の活性温度以下で仮接続し、吸排気孔が設けられた密閉容器内の静水圧下で硬化剤の活性温度以上で加熱することを特徴とする、チップ高さの異なる場合または基板の両面に実装する場合のマルチチップモジュールの実装方法。
- 基板上に複数個のチップを実装する方法であって、基板上の電極形成面と電極間に潜在性硬化剤を含有する接着剤を介在させ、基板の電極とこれに相対峙するチップの電極を位置合わせした状態で接着剤中の導電粒子もしくは電極間の直接接触により電気的接続が得られるように前記硬化剤の活性温度以下で仮接続し、この状態で導通検査および/又はチップ周囲の余剰接着剤を除去する工程を行った後、吸排気孔が設けられた密閉容器内の静水圧下で硬化剤の活性温度以上で加熱することを特徴とする、チップ高さの異なる場合または基板の両面に実装する場合のマルチチップモジュールの実装方法。
- 請求項1または請求項2において、密閉容器内の静水圧下で実装する基板が複数枚であることを特徴とするマルチチップモジュールの実装方法。
- 請求項1ないし請求項3のいずれかにおいて、加熱加圧時に厚み保持材として接着剤中に導電粒子または絶縁粒子が添加された接着剤を用いるマルチチップモジュールの実装方法。
- 請求項1ないし請求項4のいずれかにおいて、前記密閉容器に試料の出し入れ口が設けられていることを特徴とするマルチチップモジュールの実装方法。
- 請求項1ないし請求項5のいずれかにおいて、前記基板の電極とこれに相対峙する前記チップの電極を位置合わせし、前記接着剤の粘着性により前記チップを前記基板上に仮付けした状態で、前記接着剤中の前記導電粒子もしくは前記電極間の直接接触により電気的接続が得られるように前記硬化剤の活性温度以下で仮接続することを特徴とするマルチチップモジュールの実装方法。
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JP20687696A Division JP4032317B2 (ja) | 1996-08-06 | 1996-08-06 | チップ実装法 |
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US10930613B2 (en) | 2018-09-21 | 2021-02-23 | Samsung Electronics Co., Ltd. | Semiconductor package having recessed adhesive layer between stacked chips |
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JP5830847B2 (ja) * | 2010-10-21 | 2015-12-09 | 富士通株式会社 | 半導体装置の製造方法及び接合方法 |
JP2024049251A (ja) * | 2022-09-28 | 2024-04-09 | デクセリアルズ株式会社 | 接続構造体 |
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JPH0680701B2 (ja) * | 1986-03-19 | 1994-10-12 | 株式会社日立製作所 | ピン付チツプキヤリア |
JPH01199440A (ja) * | 1988-02-04 | 1989-08-10 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP3128816B2 (ja) * | 1990-11-07 | 2001-01-29 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
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US10930613B2 (en) | 2018-09-21 | 2021-02-23 | Samsung Electronics Co., Ltd. | Semiconductor package having recessed adhesive layer between stacked chips |
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