WO2010134230A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2010134230A1
WO2010134230A1 PCT/JP2010/000430 JP2010000430W WO2010134230A1 WO 2010134230 A1 WO2010134230 A1 WO 2010134230A1 JP 2010000430 W JP2010000430 W JP 2010000430W WO 2010134230 A1 WO2010134230 A1 WO 2010134230A1
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Prior art keywords
substrate
electrode
semiconductor device
sealing film
electronic component
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PCT/JP2010/000430
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English (en)
French (fr)
Inventor
櫻井大輔
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パナソニック株式会社
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and relates to a semiconductor device having a substrate on which an electronic component such as a semiconductor element is mounted and a manufacturing method thereof.
  • bump electrodes are formed by forming bump electrodes such as solder bumps on the electrode terminals of semiconductor elements such as integrated circuits, and pressing the formed bump electrodes against the connection terminals of the mounting substrate and heating them. Form a connection.
  • thermosetting the material see, for example, Patent Document 1.
  • a sealing adhesive containing flux is supplied on a substrate having a metal pattern.
  • the semiconductor element having solder bumps is positioned, pressed and heated so that the bumps and the metal pattern face each other.
  • the solder bump and the metal pattern provided on the substrate are connected, and at the same time, the adhesive is thermally cured.
  • This disclosure is intended to realize a semiconductor device with improved connection reliability between an electronic component such as a semiconductor element and a substrate.
  • This disclosure has a configuration in which the semiconductor device covers the entire surface of the substrate and the semiconductor element.
  • the exemplary semiconductor device includes a first substrate having a first substrate electrode, a first component electrode, and the first substrate electrode and the first component electrode facing each other.
  • a first electronic component mounted on the substrate, a first connection member for electrically connecting the first substrate electrode and the first component electrode, and covering the entire surface of the first substrate, A sealing film containing a flux component, and the first electronic component is entirely covered with the sealing film.
  • the example semiconductor device has a difference in expansion in the thickness direction between the sealing film and the substrate in a process where heat is applied such as reflow and a repetition of a cooling and heating cycle, as compared with a case where an electronic component such as a semiconductor element is exposed. Get smaller. Also, the difference in stress applied in the thickness direction is reduced. For this reason, the warpage of the entire semiconductor device can be further reduced, and the connection reliability between the electronic component such as a semiconductor element and the substrate can be improved.
  • the first electronic component may be a semiconductor element.
  • the first electronic component may be a plurality, and at least one may be a semiconductor element.
  • the exemplary semiconductor device further includes a second substrate mounted on the sealing film, the first substrate has a first substrate connection electrode, and the second substrate has a second substrate connection electrode.
  • the first substrate connection electrode and the second substrate connection electrode may be configured to face each other and be electrically connected via the second connection member.
  • the first substrate and the second substrate have a structure in which the first substrate and the second substrate are bonded via the sealing film without a gap, the amount of expansion and contraction in the thickness direction when heat is applied is greater than when there is a gap. Get smaller. For this reason, the warp of the semiconductor device is reduced and the connection reliability is improved. Moreover, the effect that the penetration
  • the present invention can be applied to a semiconductor device that generates a large amount of heat.
  • the heat radiating plate may be configured to be in contact with the surface of the first electronic component opposite to the first component electrode.
  • the first connecting member may be a solder or a protruding electrode formed on the solder and the first component electrode.
  • An exemplary method for manufacturing a semiconductor device includes a step (a) of attaching a sealing film containing a flux on a first substrate having a first substrate electrode, and a first formed on a first electronic component.
  • the step (b) of connecting the first connecting member on the component electrode of step (b), and embedding the first electronic component in the sealing film after the step (b), the first substrate electrode and the first electrode The step (c) of electrically connecting the connecting member 1 and the step (d) of heating and curing the sealing film after the step (c).
  • the first step The entire side surface of the electronic component is covered with the sealing film.
  • the sealing resin for sealing between the semiconductor element and the substrate and the sealing resin for covering the semiconductor element can be formed of the same material and in one step. For this reason, since there is no space and adhesion is improved as compared with the case of using a plurality of sealing films, it is possible to easily manufacture a semiconductor device that improves connection reliability.
  • An example method for manufacturing a semiconductor device includes a step (e) of connecting a second connection member on a second substrate connection electrode formed on a second substrate, a step after the step (c), and a step Prior to (d), the second connection member connected to the second substrate connection electrode is embedded in the sealing film, and the first substrate connection electrode formed on the first substrate and the second substrate connection electrode are formed.
  • the step (f) of electrically connecting the connecting member may be further included.
  • the first electronic component is plural, and at least one may be a semiconductor element.
  • the first substrate is divided into a plurality of blocks on which at least one first electronic component is mounted. It is good also as a structure.
  • the semiconductor device and the manufacturing method thereof of the present disclosure it is possible to realize a semiconductor device with improved connection reliability between an electronic component such as a semiconductor element and a substrate.
  • FIG. 6 is a cross-sectional view illustrating an exemplary semiconductor device manufacturing method in the order of steps. It is sectional drawing which shows the modification of an example semiconductor device.
  • (A)-(c) is sectional drawing which shows the modification of a semiconductor device. It is sectional drawing which shows the modification of a semiconductor device. It is sectional drawing which shows a manufacturing method in order of a process about the modification of a semiconductor device. It is sectional drawing which shows a manufacturing method in order of a process about the modification of a semiconductor device.
  • FIG. 1 shows a cross-sectional configuration of an exemplary semiconductor device.
  • a first electronic component 13 that is a semiconductor element is mounted on a first substrate 12 that is a circuit board.
  • a sealing film 14 is formed on the first substrate 12, and the first electronic component 13 is embedded in the sealing film 14.
  • the first substrate 12 may be a circuit substrate such as a glass epoxy multilayer substrate or an aramid multilayer substrate. Further, a silicon substrate or the like may be used instead of the circuit board.
  • a first substrate electrode 21 is formed on the component mounting surface of the first substrate 12.
  • An external connection electrode 22 is formed on the surface (back surface) opposite to the component mounting surface of the first substrate 12.
  • Solder balls 23 are formed on the external connection electrodes 22. The solder ball 23 may be omitted.
  • the first electronic component 13 is a semiconductor element, and a first component electrode 31 is formed on one surface.
  • the first component electrode 31 is electrically connected to the first substrate electrode 21 via the first connection member 32.
  • the first connection member 32 is a protruding electrode such as a solder bump.
  • the first electronic component 13 is embedded in the sealing film 14, and the entire side surface of the first electronic component 13 is covered with the sealing film 14. For this reason, in the process of applying heat such as reflow and the repetition of the cooling and heating cycle, the stress difference and the expansion difference in the thickness direction between the sealing resin and the substrate are reduced as compared with the case where the semiconductor element is exposed. Accordingly, warpage as a semiconductor device can be reduced, and connection reliability between an electronic component such as a semiconductor element and the substrate can be improved.
  • the sealing film 14 includes a base resin, a curing agent, an additive, an inorganic filler, and a flux component. Since it contains a flux component, it acts as a flux when the first connecting member 32 is melted and soldered to the first substrate electrode 21 and the first component electrode 31 in a heated and pressurized state. In addition, the first substrate 12 and the first electronic component 13 can be bonded and sealed by three-dimensional crosslinking by heating.
  • the base resin may be, for example, an epoxy resin, an acrylic resin, a phenol resin, a silicone resin, or a urethane resin.
  • the flux component may be, for example, a resin having a phenolic hydroxyl group, a cyclic olefin resin, malic acid, abietic acid, adipic acid, ascorbic acid, acrylic acid, citric acid, 2-furoic acid, or poly Acrylic acid or the like may be used.
  • the filler for example, an inorganic filler such as alumina or silica or an organic filler such as acrylic may be used, and the content may be 40 mass% to 70 mass%.
  • FIG. 1 As a specific example, when the linear expansion coefficient of the first substrate 12 is 10 ppm to 20 ppm and the elastic modulus is 10 GPa to 30 GPa, the linear expansion coefficient ⁇ 1 below the glass transition temperature of the sealing film 14 is 20 ppm to 40 ppm. It is desirable that the linear expansion coefficient ⁇ 2 above the glass transition temperature is 70 ppm to 120 ppm and the elastic modulus is 5 GPa to 10 GPa.
  • the size of the first substrate 12 is 15 mm ⁇ 15 mm, the thickness is 0.3 mm, and the size of the first electronic component 13 is 8 mm ⁇ 8 mm.
  • the thickness of the sealing film 14 may be set to 0.10 mm to 0.18 mm. With this configuration, the flatness of the first connecting member 32 made of solder balls can be suppressed to within 0.15 mm in the temperature range of ⁇ 50 ° C. to 150 ° C.
  • the sealing film 14 may be anything.
  • Various additives such as a curing catalyst, a colorant, an antifoaming agent, a flame retardant, and a coupling agent and a solvent may be added to the sealing film 14.
  • a thermoplastic resin may also be used.
  • FIG. 2 shows a method of manufacturing the semiconductor device according to this embodiment in the order of steps.
  • the first substrate 12 has a first substrate electrode 21 on the mounting surface and an external connection electrode 22 on the back surface.
  • the first substrate electrode 21 may be formed of an alloy of gold, nickel, and copper (AuNiCu), copper, or the like.
  • the solder balls 23 may be connected to the external connection electrodes 22, but they may not be connected.
  • the sealing film 14 may be attached using a roller or a pressure device. What is necessary is just to select suitably sticking conditions, such as normal temperature pressurization, vacuum pressurization, or heat pressurization.
  • the first electronic component 13 may be a semiconductor element formed on a semiconductor substrate, for example.
  • a first component electrode 31 is formed on the element formation surface of the semiconductor substrate.
  • a first connection member 32 made of a solder bump or the like is formed on the first component electrode 31.
  • the solder bumps may be formed by any method. For example, it may be formed by screen printing, or may be formed by plating, and is formed by a method in which solder balls are mounted in a state where flux is supplied onto the first component electrode 31 and placed in a reflow furnace. May be.
  • the material of the solder bump may be SnAg, SnAgCu, SnZn, SnZnBi, SnPb, SnBi, SnAgBiIn, or the like.
  • the first component electrode 31 may be Au, Cu, or the like, and may be formed using a sputtering method, a plating method, or the like.
  • the projection electrode (bump) which consists of gold
  • the first electronic component 13 is pressed in a heated state to perform heat pressure welding.
  • the heating temperature in this case is set to be equal to or lower than the temperature at which the first connecting member 32 melts.
  • the surface of the first electronic component 13 on which the first component electrode 31 is formed sinks more than the upper surface of the sealing film 14, and the first connection member formed on the first component electrode 31. It is preferable to pressurize until the top of 32 reaches the first substrate electrode 21 through the sealing film 14. If it does in this way, solder joining of the 1st connecting member 32 will become easy in a subsequent process.
  • the heating is performed to a temperature equal to or higher than the melting point of the solder to activate the flux component contained in the sealing film 14, and the first connection member 32 is melted and diffusion bonded to the first substrate electrode 21.
  • Solder may be precoated on the surface of the first substrate electrode 21 in advance. Pre-coating facilitates solder bonding even in the case of a large-sized substrate or a thin semiconductor element with large warpage.
  • the sealing film 14 is cured by continuing heating and heating. Then, it cools until it becomes below the freezing point of solder. Thereby, the first substrate electrode 21 and the first component electrode 31 can be electrically connected via the first connection member 32. Even after the connection is formed, it is desirable to further heat below the melting point of the solder. By this heat treatment, not only directly under the first electronic component 13 but also the curing reaction of the entire sealing film 14 is promoted, and higher reliability can be obtained.
  • a plurality of functional blocks are used by using a dicing device, a punching die device, a laser cutting device, or the like. Divide into According to this manufacturing method, a semiconductor device having the same planar dimensions of the sealing film 14 and the first substrate 12 and excellent end face accuracy can be obtained.
  • the solder may be melted and the sealing film may be cured.
  • the sealing film 14 is thermally contracted in the planar direction, the sealing film 14 is accommodated in the first substrate 12, and the external dimensions of the semiconductor device are the same as the external dimensions of the first substrate 12.
  • the semiconductor device of this embodiment uses a sheet-like sealing film 14. For this reason, it is easy to control the thickness of the sealing resin, and the occurrence of warpage due to the variation in the thickness of the sealing resin can be prevented. Therefore, high connection reliability can be realized even when miniaturization progresses.
  • the semiconductor device of this embodiment it is thinner if the surface (back surface) opposite to the surface on which the first component electrode is formed in the first electronic component 13 is exposed from the sealing film 14.
  • the number of manufacturing steps can be reduced and productivity can be improved.
  • the connection reliability is further improved when the entire first electronic component 13 is covered with the sealing film 14.
  • the second electronic device 13 is sealed on the sealing film 14 after the back surface of the first electronic component 13 is exposed from the sealing film 14.
  • a film may be attached and cured.
  • FIG. 1 shows an example in which one element is mounted on the first substrate 12. However, as shown in FIG. 3, a plurality of elements may be mounted on the first substrate 12.
  • FIG. 3 shows an example in which the first electronic component 13 includes a semiconductor element 13A, a wafer level chip size package 13B, and a chip capacitor 13C.
  • any element such as a resistance element, a coil, and a light emitting diode can be mounted.
  • the first substrate 12 When mounting a plurality of elements in this way, the first substrate 12 may be enlarged.
  • the first substrate 12 When the first substrate 12 is enlarged, it is preferable to match the linear expansion coefficient of the sealing film 14 with the linear expansion coefficient of the first substrate 12.
  • the filler filling amount may be changed.
  • the filling amount of the filler is small, the linear expansion coefficient of the sealing film 14 increases and the warp of the semiconductor device increases.
  • the filling amount of the filler is too large, the sealing film 14 becomes brittle and cracks are generated due to the tensile stress after thermosetting. For this reason, it is necessary to set the filling amount of the filler in an appropriate range.
  • the warp amount of the semiconductor device is about 0.09 mm. Due to the small amount of warpage, no defects such as open defects were found after mounting on the motherboard.
  • a heat radiating plate 15 may be provided as shown in FIG.
  • the radiator plate 15 may be formed of a material having high thermal conductivity such as stainless steel, copper, aluminum, or gold.
  • the heat radiating plate 15 may be a flat plate as shown in FIG. 4A, but may be a heat radiating plate 15B having columnar radiating fins as shown in FIG. 4B, or as shown in FIG. 4C.
  • the heat radiation plate 15C having needle-like heat radiation fins is preferable because the heat dissipation can be further enhanced.
  • the heat radiating fins may be formed integrally with the heat radiating plate main body or may be attached to the heat radiating plate main body.
  • the filler filled in the sealing film 14 is an inorganic filler such as alumina, silicon nitride, or silicon carbide having high thermal conductivity.
  • the resin containing the flux is adhered to the entire surface of the first substrate 12 with a uniform film thickness, and the first electronic component 13 can be covered. Furthermore, since the sealing film 14 and the first electronic component 13 are sandwiched between the heat dissipation plate 15 having a low linear expansion coefficient and the first substrate 12, warpage of the entire semiconductor device can be further reduced, and high connection reliability is ensured. At the same time, heat dissipation can be improved.
  • FIG. 5 shows a cross-sectional configuration of a modified example of the semiconductor device.
  • the second substrate 16 is mounted on the sealing film 14.
  • a second electronic component 17 is mounted on the mounting surface of the second substrate 16.
  • the second electronic component 17 is, for example, a semiconductor element, has a second component electrode 71, and is die-bonded on the second substrate 16 with the surface on which the second component electrode 71 is formed facing up. ing.
  • a second substrate electrode 61 is formed on the mounting surface of the second substrate 16, and the second substrate electrode 61 and the second component electrode 71 are electrically connected by a wire 72.
  • a sealing resin 18 is formed on the mounting surface of the second substrate 16 so as to cover the second electronic component 17 and the wires 72.
  • a second substrate connection electrode 65 is formed on the surface (back surface) opposite to the mounting surface of the second substrate 16.
  • a first substrate connection electrode 25 is formed on the mounting surface of the first substrate 12, and the first substrate connection electrode 25 and the second substrate connection electrode 65 face each other, and the second connection member 66. It is electrically connected via.
  • the second connection member 66 is formed of, for example, a copper ball and solder.
  • the sealing film 14 is filled between the first substrate 12 and the second substrate 16 without a gap. For this reason, the expansion and contraction amount and the thermal stress when heat is applied to the semiconductor device are reduced, and the warpage of the semiconductor device can be reduced. Therefore, high connection reliability can be ensured. Moreover, since intrusion of moisture such as water vapor can be prevented, the occurrence of defects such as corrosion and migration of the electrode portion can be suppressed. Therefore, the effect that high connection reliability can be ensured even under high temperature and high humidity can be obtained.
  • FIG. 6 shows a method of manufacturing a semiconductor device according to this modification in the order of steps.
  • the first electronic component 13 is placed on the first substrate 12, and the first substrate electrode 21 and the first component are placed.
  • the electrode 31 is connected to the first connection member 32.
  • the second electronic component 17 is mounted on the mounting surface of the second substrate 16.
  • the second electronic component 17 may be any type, but may be a memory, for example.
  • the mounting of the second electronic component 17 on the second substrate 16 may be performed by ordinary die bonding.
  • the sealing resin 18 is formed on the mounting surface of the second substrate 16 so as to cover the second electronic component 17 and the wire 72.
  • a second connection member 66 made of bumps is formed on the back surface of the second substrate 16.
  • the second connecting member 66 is, for example, supplied with solder to the second substrate connecting electrode 65 formed on the second substrate 16 by screen printing, then mounted with a copper ball, and heated using a reflow furnace or the like. May be formed.
  • the second connection member 66 is not limited to a bump made of a copper ball, but may be a stud bump made of gold or aluminum, or a plated bump made of solder, gold, gold-nickel, copper, indium, or the like. Thereafter, the second substrate 16 is mounted on the sealing film 14 so that the second substrate connection electrode 65 and the first substrate connection electrode 25 formed on the first substrate 12 face each other. .
  • the sealing film 14 is softened by heating, and the second connection member 66 pushes the sealing film 14 while contacting the first substrate connection electrode 25.
  • the second substrate 16 is pressed and pushed.
  • the first substrate connection electrode 25 is preferably precoated with solder in advance.
  • heating is performed to activate the flux component contained in the sealing film 14, and the oxide film on the electrode surface is removed.
  • solder is further heated to a melting point or higher, copper and solder are diffusion-bonded and a curing reaction of the sealing film 14 starts. Furthermore, it heats and completes the curing reaction of the sealing film 14.
  • each block is divided by a dicing blade or the like.
  • the sealing film 14 is affixed on the whole surface on the 1st board
  • substrate was demonstrated, you may affix locally only on a required part.
  • the first substrate 12 and the second substrate 16 can be easily bonded without a gap, so that the warpage of the entire semiconductor device can be reduced and high connection reliability is ensured. it can.
  • the division is performed after mounting the second substrate 16 on the first substrate 12, but the division may be performed first as shown in FIG. As shown in FIG. 7A, after mounting the first electronic component on the first substrate 12, the first substrate 12 is divided into a plurality of parts by punching using a mold. To do.
  • the second substrate 16 is aligned with respect to each portion.
  • the second substrate 16 is heated and pressed to push the second connecting member 66 into the sealing film 14, and then solder is bonded and sealed.
  • the film 14 is cured. As a result, the sealing film cures and shrinks and falls within the outer dimensions of the substrate 12.
  • a plurality of elements may be mounted as the first electronic component 13 on the first substrate 12.
  • the second electronic component 17 may be an electronic component other than a semiconductor element, and may further include a plurality of elements.
  • the example in which the second electronic component 17 is mounted on the second substrate 16 by wire bonding is shown, it may be mounted by flip chip mounting or the like.
  • a semiconductor device and a manufacturing method thereof according to the present disclosure can realize a semiconductor device having improved connection reliability between an electronic component such as a semiconductor element and a substrate, and in particular, a semiconductor device mounted with a semiconductor element or the like having a narrow pitch, and It is useful as a manufacturing method thereof.

Abstract

　半導体装置は、第１の基板電極２１を有する第１の基板１２と、第１の部品電極３１を有し、第１の基板電極２１と第１の部品電極３１とを対向させて第１の基板１２の上に搭載された第１の電子部品１３と、第１の基板電極２１と第１の部品電極３１とを電気的に接続する第１の接続部材３２と、第１の基板１２上の全面を覆い、フラックス成分を含有する封止フィルム１４とを備えている。第１の電子部品１３は側面全体が封止フィルム１４に覆われている。

Description

半導体装置及びその製造方法
　本開示は半導体装置及びその製造方法に関し、半導体素子等の電子部品が実装された基板を有する半導体装置及びその製造方法に関する。
　近年、半導体素子に設けられた回路が高密度化されるに従い、電極端子の数を多くすると共に電極端子のピッチを狭くすることが進められている。電極端子の狭ピッチ化に伴い、半導体素子を実装基板にフリップチップ実装する際に半導体素子と実装基板との間に注入する封止樹脂に対する要求が厳しくなってきている。
　通常、フリップチップ実装においては、集積回路等の半導体素子の電極端子上にはんだバンプ等の突起電極を形成し、形成した突起電極を実装基板の接続端子に対して圧接して加熱することによりバンプ接続を形成する。
　はんだバンプを用いたフリップチップ接合では、はんだ接合後にフラックスを洗浄し、封止樹脂の注入を行い、注入した封止樹脂を熱硬化する方法が知られている。この方法では、実装基板の電極上にフラックスを供給した後、はんだバンプが形成された半導体素子を位置合わせし、実装基板上に搭載する。その後リフロー炉等の加熱手段によりはんだを溶融接合した後、洗浄液に浸漬しフラックス成分を溶解洗浄する。その後、はんだ接合部の耐落下及び曲げ信頼性を強化する目的で、半導体素子と実装基板との間の空隙に、ディスペンサー等を用いて封止樹脂を注入した後、注入した封止樹脂を熱硬化させる。
　しかし、電極端子の狭ピッチ化が進展し、半導体素子と実装基板の電極と間の隙間も小さくなってきている。このため、洗浄液の循環が悪くなりフラックスが実装基板上に残り、使用環境下においてオープン不良や剥離が発生するおそれが増大している。また、空隙が狭いために毛細管現象の効果を発揮できず、封止樹脂の注入に時間を要し、生産性が低下するというお問題が生じている。
　このような不具合への対策として、フラックスを含有した封止接着材を基板上に供給した後、はんだバンプを形成した半導体素子をマウントし、加熱及び加圧手段によって、はんだ接合と同時に封止接着材を熱硬化する方法がある（例えば、特許文献１を参照。）。例えば、金属パターンを有する基板の上にフラックスを含有した封止接着材を供給する。この後、はんだバンプを有する半導体素子をバンプと金属パターンとが対向するように位置合わせをして加圧及び加熱する。これにより、はんだバンプと基板上に設けられた金属パターンとを接続すると同時に接着材を熱硬化させる。
　しかし、近年特にモバイル機器に代表される電子機器において、半導体装置の薄型化及び高機能化への要求が高まり、それに追従するため半導体素子及び回路基板の薄型化や回路基板の大型化が進められている。先に述べた方法を薄い半導体素子に適用した場合、加圧によりはみ出した封止接着材が半導体素子の裏面に回り込むおそれがある。半導体基板の熱膨張係数と封止接着剤の線膨張係数との間には差がある。このため、半導体素子の裏面に回り込んだ封止接着材が熱硬化により硬化した後、リフロー炉等により熱が加えられると半導体素子が割れるおそれがある。
　そこで、フラックスを含有した封止フィルムを基板上に載置することにより、封止接着材の量を制御しやすくし、半導体素子裏面への封止接着材の回り込みを防止する方法が提案されている（例えば、特許文献２を参照。）。
特許第２５８９２３９号明細書 特許第４０４７７５４号明細書
　しかしながら、半導体素子等の電子部品が剥き出しの状態では、リフロー炉等の熱のかかる工程後に、半導体素子の線膨張係数と回路基板の線膨張係数との差による影響を大きく受ける。このため、半導体装置の反りが大きくなり、半導体装置をマザーボードへ実装する際に、電極端子のオープン不良が発生するおそれがある。さらに、高温の使用環境と低温の使用環境とを繰り返すと、半導体素子と回路基板の線膨張係数及び弾性率の差から、接続部に大きな熱応力負荷がかかり、接続部が破断し、オープン不良が発生するおそれがある。このように、従来の半導体装置には、半導体素子と基板との接続信頼性が低いという問題があった。
　本開示は、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現できるようにすることを目的とする。
　本開示は半導体装置を、封止フィルムが基板上の全面を覆い且つ半導体素子を覆う構成とする。
　具体的に、例示の半導体装置は、第１の基板電極を有する第１の基板と、第１の部品電極を有し、第１の基板電極と第１の部品電極とを対向させて第１の基板の上に搭載された第１の電子部品と、第１の基板電極と第１の部品電極とを電気的に接続する第１の接続部材と、第１の基板上の全面を覆い、フラックス成分を含有する封止フィルムとを備え、第１の電子部品は側面全体が封止フィルムに覆われている。
　例示の半導体装置は、リフロー等の熱がかかる工程及び冷熱サイクルの繰り返し等において、半導体素子等の電子部品が剥き出しの場合と比べて、封止フィルムと基板との厚さ方向の膨張の差が小さくなる。また、厚さ方向に加わる応力の差も小さくなる。このため、半導体装置全体としての反りがさらに低減でき、半導体素子等の電子部品と基板との接続信頼性を向上させることができる。
　例示の半導体装置において、第１の電子部品は、半導体素子であればよい。また、第１の電子部品は複数であり、少なくとも１つは半導体素子である構成としてもよい。
　例示の半導体装置は、封止フィルムの上に搭載された第２の基板をさらに備え、第１の基板は第１の基板接続電極を有し、第２の基板は第２の基板接続電極を有し、第１の基板接続電極と第２の基板接続電極とは、互いに対向し且つ第２の接続部材を介して電気的に接続されている構成としてもよい。この場合、第１の基板と第２の基板とが封止フィルムを介して隙間なく接着された構造となるため、熱が加えられた際の厚さ方向の伸縮量が隙間がある場合よりも小さくなる。このため、半導体装置の反りが小さくなり、接続信頼性が向上する。また、水分の侵入を低減できるという効果も得られる。
　例示の半導体装置において、封止フィルムの上に搭載された放熱板をさらに備えていることが好ましい。このような構成とすることにより、発熱量が大きい半導体装置の場合にも適用することができる。この場合において、放熱板は第１の電子部品における第１の部品電極と反対側の面と接している構成とすればよい。
　例示の半導体装置において、第１の接続部材は、はんだであっても、はんだ及び第１の部品電極の上に形成された突起電極としてもよい。
　例示の半導体装置の製造方法は、第１の基板電極を有する第１の基板の上にフラックスを含有する封止フィルムを貼り付ける工程（ａ）と、第１の電子部品に形成された第１の部品電極の上に第１の接続部材を接続する工程（ｂ）と、工程（ｂ）よりも後に、第１の電子部品を封止フィルム中に埋設すると共に、第１の基板電極と第１の接続部材とを電気的に接続する工程（ｃ）と、工程（ｃ）よりも後に、封止フィルムを加熱して硬化する工程（ｄ）とを備え、工程（ｂ）では第１の電子部品の側面全体が封止フィルムに覆われるようにする。
　例示の半導体装置の製造方法によれば、半導体素子と基板の間を封止する封止樹脂と、半導体素子を覆う封止樹脂とを同一材料で且つ一工程で形成できる。このため、複数の封止フィルムを用いる場合に比べ空隙がなく密着性が向上するので、接続信頼性を向上する半導体装置を容易に製造することが可能となる。
　例示の半導体装置の製造方法は、第２の基板に形成された第２の基板接続電極の上に第２の接続部材を接続する工程（ｅ）と、工程（ｃ）よりも後で且つ工程（ｄ）よりも前に、第２の基板接続電極と接続された第２の接続部材を封止フィルム中に埋設すると共に、第１の基板に形成された第１の基板接続電極と第２の接続部材とを電気的に接続する工程（ｆ）とをさらに備えていてもよい。
　例示の半導体装置の製造方法において、第１の電子部品は複数であり、少なくとも１つは半導体素子としてもよい。
　例示の半導体装置の製造方法において、第１の電子部品は複数であり、工程（ｄ）よりも後に、第１の基板を少なくとも１つの第１の電子部品が搭載された複数のブロックに分割する構成としてもよい。
　本開示の半導体装置及びその製造方法によれば、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現できる。
例示の半導体装置を示す断面図である。 例示の半導体装置の製造方法を工程順に示す断面図である。 例示の半導体装置の変形例を示す断面図である。 （ａ）～（ｃ）は半導体装置の変形例を示す断面図である。 半導体装置の変形例を示す断面図である。 半導体装置の変形例について製造方法を工程順に示す断面図である。 半導体装置の変形例について製造方法を工程順に示す断面図である。
　図１は、例示の半導体装置の断面構成を示している。図１に示すように例示の半導体装置は、回路基板である第１の基板１２の上に、半導体素子である第１の電子部品１３が搭載されている。第１の基板１２の上には封止フィルム１４が形成され、第１の電子部品１３は封止フィルム１４に埋め込まれている。
　第１の基板１２は、例えば、ガラスエポキシ多層基板又はアラミド多層基板等の回路基板とすればよい。また、回路基板に代えてシリコン基板等であってもよい。第１の基板１２の部品搭載面には、第１の基板電極２１が形成されている。第１の基板１２の部品搭載面と反対側の面（裏面）には、外部接続電極２２が形成されている。外部接続電極２２には、はんだボール２３が形成されている。はんだボール２３はなくてもかまわない。
　第１の電子部品１３は半導体素子であり、一の面に第１の部品電極３１が形成されている。第１の部品電極３１は、第１の接続部材３２を介して第１の基板電極２１と電気的に接続されている。第１の接続部材３２は、はんだバンプ等の突起電極である。第１の電子部品１３は、封止フィルム１４中に埋設されており、第１の電子部品１３の側面全体が封止フィルム１４により覆われている。このため、リフロー等の熱がかかる工程及び冷熱サイクルの繰り返しにおいて、半導体素子が剥き出しの場合と比較し、封止樹脂と基板で厚み方向にかかる応力差、膨張差が少なくなる。従って、半導体装置としての反りが低減でき、半導体素子などの電子部品と基板との接続信頼性を向上させることができる。
　封止フィルム１４は、ベース樹脂、硬化剤、添加剤、無機フィラー及びフラックス成分を含む。フラックス成分を含むため、加熱加圧した状態で第１の接続部材３２を溶融して第１の基板電極２１と第１の部品電極３１とをはんだ接合する際に、フラックスとして作用する。また、加熱することにより三次元架橋し、第１の基板１２と第１の電子部品１３とを接着封止することができる。
　ベース樹脂は、例えば、エポキシ樹脂、アクリル樹脂、フェノール樹脂、シリコーン樹脂又はウレタン樹脂等とすればよい。また、フラックス成分は、例えば、フェノール性水酸基を有する樹脂、環状オレフィン系樹脂、リンゴ酸、アビエチン酸、アジピン酸、アスコルビン酸、アクリル酸、クエン酸、２－フロイック酸（2-furoic acid）又はポリアクリル酸等とすればよい。フィラーには、例えばアルミナ若しくはシリカ等の無機フィラー又はアクリル等の有機フィラーを用いればよく、含有率は４０質量％～７０質量％とすればよい。
　封止フィルム１４は、第１の基板１２及び第１の電子部品１３の材質及び大きさ等に応じて最適な特性となるように選択すればよい。具体的な一例を挙げると、第１の基板１２の線膨張係数が１０ｐｐｍ～２０ｐｐｍで、弾性率が１０ＧＰａ～３０ＧＰａの場合、封止フィルム１４のガラス転位温度以下の線膨張係数α１を２０ｐｐｍ～４０ｐｐｍとし、ガラス転位温度以上の線膨張係数α２を７０ｐｐｍ～１２０ｐｐｍとし、弾性率を５ＧＰａ～１０ＧＰａとすることが望ましい。封止フィルムの厚さの具体的な一例を挙げると、第１の基板１２のサイズが１５ｍｍ×１５ｍｍで、厚さが０．３ｍｍであり、第１の電子部品１３のサイズが８ｍｍ×８ｍｍで、厚さが０．１０ｍｍｍであり、第１の接続部材３２の高さが０．０５ｍｍの場合、封止フィルム１４の厚さを０．１０ｍｍ～０．１８ｍｍとすればよい。この構成により、－５０℃～１５０℃までの温度範囲において、はんだボールからなる第１の接続部材３２の平坦度を０．１５ｍｍ以内に抑えることができた。
　未硬化状態のシート性、溶融粘度、酸化皮膜除去性及び硬化性のバランスがとれれば、封止フィルム１４はどのようなものであってもよい。封止フィルム１４に、硬化触媒、着色料、消泡剤、難燃剤、カップリング剤等の各種添加剤及び溶剤を添加してもかまわない。また、熱可塑性樹脂であってもよい。
　図２は、本実施形態に係る半導体装置の製造方法を工程順に示している。まず、図２（ａ）に示すように、第１の基板１２の搭載面の上に封止フィルム１４を貼り付けた後、封止フィルム１４の上に第１の電子部品１３を載置する。
　第１の基板１２は、搭載面に第１の基板電極２１を有し、裏面に外部接続電極２２を有する。第１の基板電極２１は、金とニッケルと銅との合金（ＡｕＮｉＣｕ）又は銅等により形成すればよい。外部接続電極２２には、はんだボール２３を接続すればよいが、なくてもよい。封止フィルム１４の貼り付けは、ローラー又は加圧装置等を用いて行えばよい。常温加圧、真空加圧又は加熱加圧等貼り付け条件は適宜選択すればよい。
　第１の電子部品１３は、例えば半導体基板に形成された半導体素子とすればよい。半導体基板の素子形成面の上に第１の部品電極３１が形成されている。第１の部品電極３１の上には、はんだバンプ等からなる第１の接続部材３２が形成されている。はんだバンプはどのような方法で形成してもよい。例えば、スクリーン印刷により形成してもよく、めっき法により形成してもよく、フラックスを第１の部品電極３１の上に供給した状態ではんだボールを搭載し、リフロー炉に投入する方法により形成してもよい。なお、はんだバンプの材質は、ＳｎＡｇ、ＳｎＡｇＣｕ、ＳｎＺｎ、ＳｎＺｎＢｉ、ＳｎＰｂ、ＳｎＢｉ又はＳｎＡｇＢｉＩｎ等とすればよい。また、第１の部品電極３１は、Ａｕ又はＣｕ等とすればよく、スパッタリング法又はめっき法等を用いて形成すればよい。なお、第１の部品電極３１の上に、金、銅又はインジウム等からなる突起電極（バンプ）をあらかじめ形成した後、その上にはんだバンプを形成してもよい。
　次に、図２（ｂ）に示すように、第１の電子部品１３を加熱した状態で押圧し、熱圧接を行う。この場合の加熱温度は、第１の接続部材３２が溶融する温度以下とする。また、第１の電子部品１３における第１の部品電極３１が形成された面が、封止フィルム１４の上面よりも沈み込み、第１の部品電極３１の上に形成された第１の接続部材３２の頭頂部が封止フィルム１４を突き破って第１の基板電極２１に届くまで加圧することが好ましい。このようにすれば、後の工程において第１の接続部材３２のはんだ接合が容易となる。次に、はんだの融点以上まで昇温加熱を行い、封止フィルム１４中に含まれるフラックス成分を活性化させると共に、第１の接続部材３２を溶融させて第１の基板電極２１と拡散接合する。第１の基板電極２１の表面にあらかじめはんだをプリコートしてもよい。プリコートにより、大型基板又は反りが大きい薄型半導体素子の場合にもはんだ接合が容易となる。続いて、昇温加熱を継続することにより、封止フィルム１４の硬化を行う。その後、はんだの凝固点以下になるまで冷却を行う。これにより、第１の基板電極２１と第１の部品電極３１とを第１の接続部材３２を介して電気的に接続できる。なお、接続が形成された後もさらにはんだの融点以下の加熱を行うことが望ましい。この加熱処理により、第１の電子部品１３の直下だけでなく封止フィルム１４全体の硬化反応が促進され、より高い信頼性が得られるようになる。
　次に、第１の基板１２に複数個の機能ブロックを形成した場合には、図２（ｃ）に示すように、ダイシング装置、打ち抜き金型装置又はレーザ切断装置等を用いて複数の機能ブロックに分割する。この製造方法によれば、封止フィルム１４と第１の基板１２の平面寸法が同一で端面精度に優れた半導体装置を得られる。
　なお、第１の基板１２を分割した後に、はんだの溶融及び封止フィルムの硬化を行ってもよい。この場合には、封止フィルム１４が平面方向に熱収縮するため、第１の基板１２の内部に納まり、半導体装置の外形寸法は第１の基板１２の外形寸法と同一となる。
　本実施形態の半導体装置は、シート状の封止フィルム１４を用いている。このため、封止樹脂の厚さが制御しやすく、封止樹脂の厚さのばらつきによる反りの発生を防ぐことができる。従って、微細化が進んだ場合でも高い接続信頼性を実現することができる。
　以上の製造方法により製造した半導体装置を、断面研磨により断面解析した結果、はんだ接合部と封止フィルム１４との密着性、第１の電子部品１３における第１の部品電極３１の形成面と封止フィルム１４との密着性及び第１の基板１２における第１の基板電極２１の形成面と封止フィルム１４との密着性はいずれも良好であった。また、温度８５℃、湿度８５％の条件下でストレス試験を行ったところ、１０００サイクルにおいても安定した接続抵抗を確保することができた。このように、本実施形態の半導体装置は、フラックスを含む封止フィルムを用いることにより、均一な厚さの封止樹脂層を第１の基板１２上の全面に形成することが容易にでき、半導体装置全体の反りを低減でき、高い接続信頼性を確保できる。
　なお、本実施形態の半導体装置において、第１の電子部品１３における第１の部品電極が形成された面と反対側の面（裏面）を封止フィルム１４から露出するようにした方が、薄型化でき製造工程も少なくなり生産性を向上させることができる。但し、第１の電子部品１３の全体が封止フィルム１４に覆われるようにした方が、より接続信頼性が向上するという利点がある。第１の電子部品１３の全体を樹脂封止する場合には、第１の電子部品１３の裏面が封止フィルム１４から露出する状態とした後、封止フィルム１４の上に第２の封止フィルムを貼り付けて硬化させればよい。
　図１においては、第１の基板１２の上に、１つの素子が搭載されている例を示している。しかし、図３に示すように、第１の基板１２の上に複数の素子が搭載されていてもよい。図３は、第１の電子部品１３が半導体素子１３Ａと、ウェハレベルチップサイズパッケージ１３Ｂと、チップコンデンサー１３Ｃとを含む例を示している。この他、抵抗素子、コイル及び発光ダイオード等のどのような素子を搭載することも可能である。
　このように複数の素子を搭載する場合には、第１の基板１２が大型化する場合がある。第１の基板１２が大型化した場合には、封止フィルム１４の線膨張係数と第１の基板１２の線膨張係数を合わせるようにすることが好ましい。封止フィルム１４の線膨張係数を調整するためには、フィラーの充填量を変化させればよい。フィラーの充填量が少ないと封止フィルム１４の線膨張係数が大きくなり半導体装置の反りが大きくなる。一方、フィラーの充填量が多すぎると封止フィルム１４がもろくなり、熱硬化後の引っ張り応力により割れが発生する。このため、フィラーの充填量は適切な範囲に設定する必要がある。例えば、第１の基板１２のサイズが２０ｍｍ×２０ｍｍの場合に、封止フィルム１４のフィラー充填量を５０質量％～６０質量％とすると、半導体装置の反り量は約０．０９ｍｍとなった。反り量が小さいため、マザーボードへ実装した後に、オープン不良等の不具合は認められなかった。
　また、第１の電子部品１３が高速演算処理チップのような発熱量が大きい素子の場合には、図４に示すように放熱板１５を設けてもよい。放熱板１５は、ステンレス、銅、アルミニウム又は金等の熱伝導率の高い材料により形成すればよい。また、放熱板１５は図４（ａ）に示すように平板としてもよいが、図４（ｂ）に示すような柱状の放熱フィン有する放熱板１５Ｂとしたり、図４（ｃ）に示すように、針状の放熱フィンを有する放熱板１５Ｃとしたりすれば、さらに放熱性を高くすることができ好ましい。放熱フィンは放熱板本体と一体に形成しても、放熱板本体に貼り付けてもよい。
　放熱性を要求される場合には、封止フィルム１４に充填するフィラーを、熱伝導性が高いアルミナ、窒化珪素又は炭化珪素等の無機フィラーとすることが好ましい。
　このような構成とすれば、フラックスを含む樹脂が均一な膜厚で第１の基板１２上の全面に接着され、第１の電子部品１３を覆うことができる。さらに、線膨張係数が低い放熱板１５と第１の基板１２とにより封止フィルム１４及び第１の電子部品１３を挟み込むので、半導体装置全体の反りをさらに低減でき、高い接続信頼性を確保すると共に放熱性も向上させることができる。
　図５は半導体装置の変形例についての断面構成を示している。図５において図１と同一の構成要素には同一の符号を附すことにより説明を省略する。本変形例は、封止フィルム１４の上に第２の基板１６が搭載されている。第２の基板１６の搭載面には第２の電子部品１７が搭載されている。第２の電子部品１７は、例えば半導体素子であり、第２の部品電極７１を有し、第２の部品電極７１が形成された面を上にして第２の基板１６の上にダイボンディングされている。第２の基板１６の搭載面には、第２の基板電極６１が形成され、第２の基板電極６１と第２の部品電極７１とは、ワイヤ７２により電気的に接続されている。第２の基板１６の搭載面の上には、第２の電子部品１７及びワイヤ７２を覆うように封止樹脂１８が形成されている。
　第２の基板１６の搭載面と反対側の面（裏面）には、第２の基板接続電極６５が形成されている。第１の基板１２の搭載面には、第１の基板接続電極２５が形成されており、第１の基板接続電極２５と第２の基板接続電極６５とは対向し、第２の接続部材６６を介して電気的に接続されている。第２の接続部材６６は、例えば、銅ボールとはんだとにより形成されている。
　本変形例は、第１の基板１２と第２の基板１６との間に隙間なく封止フィルム１４が充填されている。このため、半導体装置に熱が加わった際の膨張及び収縮量並びに熱応力が小さくなり、半導体装置の反りを低減できる。従って、高い接続信頼性を確保することが可能となる。また、水蒸気等の水分の侵入を防ぐことができるので、電極部の腐食及びマイグレーション等の不具合の発生を抑えることができる。従って、高温高湿下においても、高い接続信頼性を確保できるという効果も得られる。
　次に、本変形例の半導体装置の製造方法について説明する。図６は、本変形例に係る半導体装置の製造方法を工程順に示している。まず、先に図２（ａ）及び（ｂ）に示したようにして、第１の基板１２の上に第１の電子部品１３を載置し、第１の基板電極２１と第１の部品電極３１とを第１の接続部材３２を介して接続する。
　次に、図６（ａ）に示すように、まず、第２の基板１６の搭載面の上に第２の電子部品１７を搭載する。第２の電子部品１７はどのようなものでもよいが、例えばメモリ等とすればよい。第２の電子部品１７の第２の基板１６への搭載は通常のダイボンディングにより行えばよい。続いて、第２の電子部品１７及びワイヤ７２を覆うように、第２の基板１６の搭載面の上に封止樹脂１８を形成する。次に、第２の基板１６の裏面にバンプからなる第２の接続部材６６を形成する。第２の接続部材６６は、例えば、第２の基板１６に形成された第２の基板接続電極６５にスクリーン印刷によりはんだを供給した後、銅ボールを搭載し、リフロー炉等を用いて加熱して形成すればよい。なお、第２の接続部材６６は銅ボールからなるバンプに限らず、金又はアルミニウム等からなるスタッドバンプ、はんだ、金、金―ニッケル、銅又はインジウム等からなるめっきバンプとしてもよい。この後、第２の基板接続電極６５と、第１の基板１２に形成された第１の基板接続電極２５とが対向するように、第２の基板１６を封止フィルム１４の上に搭載する。
　次に、図６（ｂ）に示すように、加熱により封止フィルム１４を軟化させ、第２の接続部材６６が封止フィルム１４を押しのけながら、第１の基板接続電極２５と接触するまで第２の基板１６を加圧して押し込む。なお、第１の基板接続電極２５にはあらかじめはんだをプリコートしておくことが好ましい。続いて、加熱を行い、封止フィルム１４に含まれるフラックス成分を活性化し、電極表面の酸化皮膜を除去する。さらにはんだの融点以上まで加熱すると、銅とはんだが拡散接合されると共に、封止フィルム１４の硬化反応が始まる。さらに、加熱し封止フィルム１４の硬化反応を完了させる。
　次に、図６（ｃ）に示すように、ブロック毎にダイシングブレード等により分割する。
　なお、封止フィルム１４を第１の基板上の全面に貼り付ける場合について説明したが、必要な部分のみに局所的に貼り付けてもかまわない。このように、本変形例の製造方法によれば、第１の基板１２と第２の基板１６とが容易に隙間なく接着できるので、半導体装置全体の反りが低減でき、高い接続信頼性を確保できる。
　また、第１の基板１２の上に第２の基板１６を搭載した後、分割を行ったが、図７に示すように、先に分割を行ってもよい。図７（ａ）に示すように、第１の基板１２の上に第１の電子部品を搭載した後、金型を用いて打ち抜きを行うことにより、第１の基板１２を複数の部分に分割する。
　次に、図７（ｂ）に示すように、各部分に対して、第２の基板１６を位置合わせする。次に、図７（ｃ）に示すように、第２の基板１６を加熱加圧することにより、第２の接続部材６６を封止フィルム１４中に押し込んだ後、はんだを接合すると共に、封止フィルム１４の硬化を行う。これにより、封止フィルムは硬化収縮し、基板１２の外形寸法内に収まる。
　本変形例の場合においても、第１の基板１２の上に第１の電子部品１３として複数の素子が搭載されていてもよい。また、第２の電子部品１７は、半導体素子以外の電子部品であってもよく、さらに複数の素子を含む構成としてもよい。第２の電子部品１７をワイヤボンディングにより第２の基板１６に搭載する例を示したが、フリップチップ実装等により搭載してもよい。
　本開示に係る半導体装置及びその製造方法は、半導体素子等の電子部品と基板との接続信頼性を向上させた半導体装置を実現でき、特に狭ピッチ化された半導体素子等を搭載した半導体装置及びその製造方法等として有用である。
１２　　　第１の基板
１３　　　第１の電子部品
１３Ａ　　半導体素子
１３Ｂ　　ウェハレベルチップサイズパッケージ
１３Ｃ　　チップコンデンサー
１４　　　封止フィルム
１５　　　放熱板
１６　　　第２の基板
１７　　　第２の電子部品
１８　　　封止樹脂
２１　　　第１の基板電極
２２　　　外部接続電極
２３　　　ボール
２５　　　第１の基板接続電極
３１　　　第１の部品電極
３２　　　第１の接続部材
６１　　　第２の基板電極
６５　　　第２の基板接続電極
６６　　　第２の接続部材
７１　　　第２の部品電極
７２　　　ワイヤ

Claims (12)

  1. 　半導体装置は、
    　第１の基板電極を有する第１の基板と、
    　第１の部品電極を有し、前記第１の基板電極と前記第１の部品電極とを対向させて前記第１の基板の上に搭載された第１の電子部品と、
    　前記第１の基板電極と前記第１の部品電極とを電気的に接続する第１の接続部材と、
    　前記第１の基板上の全面を覆い、フラックス成分を含有する封止フィルムとを備え、
    　前記第１の電子部品は、側面全体が前記封止フィルムに覆われている。
  2. 　請求項１に記載の半導体装置において、
    　前記第１の電子部品は、半導体素子である。
  3. 　請求項１に記載の半導体装置において、
    　前記第１の電子部品は複数であり、少なくとも１つは半導体素子である。
  4. 　請求項１に記載の半導体装置は、
    　前記封止フィルムの上に搭載された第２の基板をさらに備え、
    　前記第１の基板は第１の基板接続電極を有し、
    　前記第２の基板は第２の基板接続電極を有し、
    　前記第１の基板接続電極と前記第２の基板接続電極とは、互いに対向し且つ第２の接続部材を介して電気的に接続されている。
  5. 　請求項１に記載の半導体装置は、
    　前記封止フィルムの上に搭載された放熱板をさらに備えている。
  6. 　請求項５に記載の半導体装置において、
    　前記放熱板は、前記第１の電子部品における前記第１の部品電極と反対側の面と接している。
  7. 　請求項１に記載の半導体装置において、
    　前記第１の接続部材は、はんだである。
  8. 　請求項１に記載の半導体装置において、
    　前記第１の接続部材は、はんだ及び前記第１の部品電極の上に形成された突起電極からなる。
  9. 　半導体装置の製造方法は、
    　第１の基板電極を有する第１の基板の上にフラックスを含有する封止フィルムを貼り付ける工程（ａ）と、
    　第１の電子部品に形成された第１の部品電極の上に第１の接続部材を接続する工程（ｂ）と、
    　前記工程（ｂ）よりも後に、前記第１の電子部品を前記封止フィルム中に埋設すると共に、前記第１の基板電極と前記第１の接続部材とを電気的に接続する工程（ｃ）と、
    　前記工程（ｃ）よりも後に、前記封止フィルムを加熱して硬化する工程（ｄ）とを備え、
    　前記工程（ｃ）では、前記第１の電子部品の側面全体が前記封止フィルムに覆われるようにする。
  10. 　請求項９に記載の半導体装置の製造方法は、
    　第２の基板に形成された第２の基板接続電極の上に第２の接続部材を接続する工程（ｅ）と、
    　前記工程（ｃ）よりも後で且つ前記工程（ｄ）よりも前に、前記第２の基板接続電極と接続された前記第２の接続部材を前記封止フィルム中に埋設すると共に、前記第１の基板に形成された第１の基板接続電極と前記第２の接続部材とを電気的に接続する工程（ｆ）とをさらに備えている。
  11. 　請求項９に記載の半導体装置の製造方法において、
    　前記第１の電子部品は複数であり、少なくとも１つは半導体素子である。
  12. 　請求項９に記載の半導体装置の製造方法において、
    　前記第１の電子部品は複数であり、
    　前記工程（ｄ）よりも後に、前記第１の基板を少なくとも１つの第１の電子部品が搭載された複数のブロックに分割する。
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