JP5770852B2 - ファインピッチ電気相互接続体を有する半導体ダイ - Google Patents
ファインピッチ電気相互接続体を有する半導体ダイ Download PDFInfo
- Publication number
- JP5770852B2 JP5770852B2 JP2013533871A JP2013533871A JP5770852B2 JP 5770852 B2 JP5770852 B2 JP 5770852B2 JP 2013533871 A JP2013533871 A JP 2013533871A JP 2013533871 A JP2013533871 A JP 2013533871A JP 5770852 B2 JP5770852 B2 JP 5770852B2
- Authority
- JP
- Japan
- Prior art keywords
- interconnect
- assembly
- die
- conductive
- polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
- H10W70/6523—Cross-sectional shapes for connecting to pads at different heights at the same side of the package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
- H10W70/6528—Cross-sectional shapes of the portions that connect to chips, wafers or package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01265—Thermally treating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
- H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
- H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
- H10W72/01938—Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01971—Cleaning, e.g. oxide removal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/221—Structures or relative sizes
- H10W72/225—Bumps having a filler embedded in a matrix
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/231—Shapes
- H10W72/234—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39331110P | 2010-10-14 | 2010-10-14 | |
| US61/393,311 | 2010-10-14 | ||
| US13/243,877 | 2011-09-23 | ||
| US13/243,877 US8829677B2 (en) | 2010-10-14 | 2011-09-23 | Semiconductor die having fine pitch electrical interconnects |
| PCT/US2011/053294 WO2012050812A2 (en) | 2010-10-14 | 2011-09-26 | Semiconductor die having fine pitch electrical interconnects |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013539925A JP2013539925A (ja) | 2013-10-28 |
| JP2013539925A5 JP2013539925A5 (enExample) | 2015-05-07 |
| JP5770852B2 true JP5770852B2 (ja) | 2015-08-26 |
Family
ID=45938854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013533871A Expired - Fee Related JP5770852B2 (ja) | 2010-10-14 | 2011-09-26 | ファインピッチ電気相互接続体を有する半導体ダイ |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US8829677B2 (enExample) |
| EP (1) | EP2628174A2 (enExample) |
| JP (1) | JP5770852B2 (enExample) |
| KR (1) | KR20130142132A (enExample) |
| CN (1) | CN103283008B (enExample) |
| TW (1) | TWI485827B (enExample) |
| WO (1) | WO2012050812A2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8829677B2 (en) | 2010-10-14 | 2014-09-09 | Invensas Corporation | Semiconductor die having fine pitch electrical interconnects |
| US8587088B2 (en) | 2011-02-17 | 2013-11-19 | Apple Inc. | Side-mounted controller and methods for making the same |
| WO2014032702A1 (en) * | 2012-08-28 | 2014-03-06 | Osram Opto Semiconductors Gmbh | Light-emitting device and method for manufacturing a light- emitting device |
| US10600755B2 (en) * | 2017-08-10 | 2020-03-24 | Amkor Technology, Inc. | Method of manufacturing an electronic device and electronic device manufactured thereby |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5891761A (en) | 1994-06-23 | 1999-04-06 | Cubic Memory, Inc. | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform |
| US6080596A (en) | 1994-06-23 | 2000-06-27 | Cubic Memory Inc. | Method for forming vertical interconnect process for silicon segments with dielectric isolation |
| US5657206A (en) | 1994-06-23 | 1997-08-12 | Cubic Memory, Inc. | Conductive epoxy flip-chip package and method |
| US5675180A (en) | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
| US6124633A (en) | 1994-06-23 | 2000-09-26 | Cubic Memory | Vertical interconnect process for silicon segments with thermally conductive epoxy preform |
| US6255726B1 (en) | 1994-06-23 | 2001-07-03 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments with dielectric isolation |
| US6271598B1 (en) | 1997-07-29 | 2001-08-07 | Cubic Memory, Inc. | Conductive epoxy flip-chip on chip |
| US6803303B1 (en) | 2002-07-11 | 2004-10-12 | Micron Technology, Inc. | Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts |
| US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
| US7245021B2 (en) | 2004-04-13 | 2007-07-17 | Vertical Circuits, Inc. | Micropede stacked die component assembly |
| US7215018B2 (en) | 2004-04-13 | 2007-05-08 | Vertical Circuits, Inc. | Stacked die BGA or LGA component assembly |
| JP4693619B2 (ja) * | 2004-12-17 | 2011-06-01 | 株式会社半導体エネルギー研究所 | 導電層を有する基板の作製方法及び半導体装置の作製方法 |
| JP4952915B2 (ja) * | 2007-03-08 | 2012-06-13 | セイコーエプソン株式会社 | インク層の転写方法および電子装置の製造方法 |
| WO2008115744A1 (en) | 2007-03-16 | 2008-09-25 | Vertical Circuits, Inc. | Vertical electrical interconnect formed on support prior to die mount |
| US8723332B2 (en) | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
| TWI473183B (zh) | 2007-06-19 | 2015-02-11 | 英維瑟斯公司 | 可堆疊的積體電路晶片的晶圓水平表面鈍化 |
| US7750471B2 (en) | 2007-06-28 | 2010-07-06 | Intel Corporation | Metal and alloy silicides on a single silicon wafer |
| US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
| US8703605B2 (en) * | 2007-12-18 | 2014-04-22 | Byung Chun Yang | High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability |
| US7843046B2 (en) | 2008-02-19 | 2010-11-30 | Vertical Circuits, Inc. | Flat leadless packages and stacked leadless package assemblies |
| JP5763924B2 (ja) | 2008-03-12 | 2015-08-12 | インヴェンサス・コーポレーション | ダイアセンブリを電気的に相互接続して取り付けられたサポート |
| US9153517B2 (en) | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
| US8829677B2 (en) | 2010-10-14 | 2014-09-09 | Invensas Corporation | Semiconductor die having fine pitch electrical interconnects |
| FR2933425B1 (fr) * | 2008-07-01 | 2010-09-10 | Alchimer | Procede de preparation d'un film isolant electrique et application pour la metallisation de vias traversants |
| JP2010034119A (ja) * | 2008-07-25 | 2010-02-12 | Panasonic Corp | 半導体装置 |
| JP5963671B2 (ja) | 2009-06-26 | 2016-08-03 | インヴェンサス・コーポレーション | ジグザクの構成でスタックされたダイに関する電気的相互接続 |
| TWI544604B (zh) | 2009-11-04 | 2016-08-01 | 英維瑟斯公司 | 具有降低應力電互連的堆疊晶粒總成 |
-
2011
- 2011-09-23 US US13/243,877 patent/US8829677B2/en not_active Expired - Fee Related
- 2011-09-26 CN CN201180059481.8A patent/CN103283008B/zh not_active Expired - Fee Related
- 2011-09-26 JP JP2013533871A patent/JP5770852B2/ja not_active Expired - Fee Related
- 2011-09-26 WO PCT/US2011/053294 patent/WO2012050812A2/en not_active Ceased
- 2011-09-26 KR KR1020137012495A patent/KR20130142132A/ko not_active Ceased
- 2011-09-26 EP EP11833001.8A patent/EP2628174A2/en not_active Withdrawn
- 2011-09-30 TW TW100135584A patent/TWI485827B/zh not_active IP Right Cessation
-
2014
- 2014-09-08 US US14/480,373 patent/US20150056753A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013539925A (ja) | 2013-10-28 |
| CN103283008B (zh) | 2016-02-24 |
| KR20130142132A (ko) | 2013-12-27 |
| US20150056753A1 (en) | 2015-02-26 |
| EP2628174A2 (en) | 2013-08-21 |
| US8829677B2 (en) | 2014-09-09 |
| WO2012050812A8 (en) | 2013-06-27 |
| TWI485827B (zh) | 2015-05-21 |
| WO2012050812A3 (en) | 2012-06-14 |
| US20120248607A1 (en) | 2012-10-04 |
| CN103283008A (zh) | 2013-09-04 |
| WO2012050812A2 (en) | 2012-04-19 |
| TW201232732A (en) | 2012-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11270990B2 (en) | Contoured package-on-package joint | |
| JP4428337B2 (ja) | 半導体装置の製造方法 | |
| TWI402939B (zh) | 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法 | |
| CN103904050B (zh) | 封装基板、封装基板制作方法及封装结构 | |
| US20100320560A1 (en) | Metallic Bump Structure Without Under Bump Metallurgy And a Manufacturing Method Thereof | |
| US10388607B2 (en) | Microelectronic devices with multi-layer package surface conductors and methods of their fabrication | |
| TWI344199B (en) | Inter-connecting structure for semiconductor device package and method of the same | |
| JP7347440B2 (ja) | 半導体パッケージ用配線基板の製造方法 | |
| JP5770852B2 (ja) | ファインピッチ電気相互接続体を有する半導体ダイ | |
| JP2011528507A (ja) | 薄いメタルコンタクトを具備する集積回路をパッケージングする方法及びシステム | |
| KR20130037204A (ko) | 고정된 언더필을 구비한 회로 기판 | |
| TW201145466A (en) | Electronic component for wiring and method of manufacturing the same | |
| CN104091790A (zh) | 一种半导体封装基板结构及其制作方法 | |
| CN1531043A (zh) | 电子装置的制造方法及芯片载架 | |
| US10939561B1 (en) | Wiring structure and method of manufacturing the same | |
| US20140183726A1 (en) | Package substrate, method for manufacturing the same, and package on package substrate | |
| JP5466096B2 (ja) | 半導体装置及びその製造方法 | |
| US12094727B2 (en) | Method forming a semiconductor package device | |
| JP7528578B2 (ja) | 支持体付き基板ユニット、基板ユニット、半導体装置、および、支持体付き基板ユニットの製造方法 | |
| TWI917995B (zh) | 包括具有合金阻障層的內連線的中介物模組、包括中介物模組的封裝結構及其製造方法 | |
| CN113451161B (zh) | 半导体封装方法及半导体封装结构 | |
| TW202545025A (zh) | 包括具有合金阻障層的內連線的中介物模組、包括中介物模組的封裝結構及其製造方法 | |
| CN1791979A (zh) | 半导体芯片安装体及其制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140911 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140911 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20140911 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20141203 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141205 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150305 |
|
| A524 | Written submission of copy of amendment under article 19 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A524 Effective date: 20150320 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150602 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150625 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5770852 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| LAPS | Cancellation because of no payment of annual fees |