JP5741188B2 - 接続構造体の製造方法 - Google Patents
接続構造体の製造方法 Download PDFInfo
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- JP5741188B2 JP5741188B2 JP2011098967A JP2011098967A JP5741188B2 JP 5741188 B2 JP5741188 B2 JP 5741188B2 JP 2011098967 A JP2011098967 A JP 2011098967A JP 2011098967 A JP2011098967 A JP 2011098967A JP 5741188 B2 JP5741188 B2 JP 5741188B2
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- electronic component
- wiring board
- adhesive film
- curing temperature
- heating
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- Wire Bonding (AREA)
Description
工程(a)
配線基板の表面に、第1接着フィルムを介して第1電子部品を仮設置する工程;
工程(b)
配線基板の裏面に、第1接着フィルムの硬化温度よりも低い硬化温度を有する第2接着フィルムを介して第2電子部品を仮設置する工程;
工程(c)
第1電子部品及び第2電子部品が仮設置された配線基板を、圧着受け台に載置する工程;及び
工程(d)
第1電子部品を、配線基板に対して第1電子部品側から加熱加圧ツールで押圧しながら加熱することにより、配線基板の表面及び裏面に第1電子部品及び第2電子部品をそれぞれ一括で実装する工程
を有することを特徴とする製造方法、及びこの製造方法により製造された接続構造体を提供する。
まず、図1に示すように、配線基板1の表面に、第1接着フィルム2を介して第1電子部品3を仮設置する。具体的には、ステージ10上に、表面電極1aと裏面電極1bとを有する配線基板1を載せ、表面電極1a上に、第1接着フィルム2をアライメントして仮貼し、その上にバンプ3aを有する第1電子部品3をアライメントして仮設置する。
次に、図2に示すように、配線基板1の裏面に、第1接着フィルム2の硬化温度よりも低い硬化温度を有する第2接着フィルム4を介して第2電子部品5を仮設置する。具体的には、ステージ10上において、配線基板1の裏面電極1b上に、第2接着フィルム4をアライメントして仮貼し、その上にバンプ5aを有する第2電子部品5をアライメントして仮設置する。
次に、図4に示すように、第1電子部品3及び第2電子部品5が仮設置された配線基板1を、ゴムなどの弾性材料から形成された配線基板載置面21を有する圧着受け台20に載置する。このような圧着受け台20としては、特開2007−227622号公報に開示されているものを採用することができる。即ち、圧着受け台20は、金属やセラミックスからなる受け台本体22と、被圧着物が載置される側に配置される弾性受け部23とから構成され、その表面が配線基板載置面21となっているものである。ここで、本発明において、弾性材料とは、好ましくはゴム硬度が10〜80のエラストマーを意味する。
最後に、第1電子部品3を、配線基板1に対して第1電子部品3側から、ゴムなどの弾性材料から形成されている押圧面31を有する加熱加圧ツール30(図5)で押圧しながら加熱することにより、図6に示すように配線基板1の表面及び裏面に第1電子部品3及び第2電子部品5をそれぞれ一括で実装する。これにより図7に示す接続構造体100が得られる。
表2に示した硬化温度を示すNCFを用意した。それとは別に、バンプピッチ85μm、バンプ数272のペリフェラル配置の金スタッドバンプ(“Auスタッド”と略する場合がある)又は銅ピラー/ハンダキャップバンプ(“Cu/ハンダ”と略する場合がある)が設けられた試験用ICチップ(6.3mm×6.3mm×0.2厚)を用意した。また、20μm厚のハンダ表面層が形成された電極パッド(Au/NiメッキCuベース)を両面に有するガラスエポキシ両面配線基板(FR4、日立化成工業(株):38mm×38mm×0.6mm厚)を用意した。
1a 表面電極
1b 裏面電極
2 第1接着フィルム
3 第1電子部品
3a バンプ
4 第2接着フィルム
5 第2電子部品
5a バンプ
10 ステージ
20 圧着受け台
21 配線基板載置面
22 受け台本体
23 弾性受け部
30 加熱加圧ツール
31 押圧面
32 押圧本体
33 弾性押圧部
34 側部
35 保護シート
100 接続構造体
40 ICチップ
41 貫通電極
42 フロントバンプ
43 バックバンプ
400 積層型の電子部品
Claims (8)
- 配線基板と、その表面にフリップチップ実装された第1電子部品と、裏面にフリップチップ実装された第2電子部品とを含む接続構造体の製造方法であって、以下の工程(a)〜(d):
工程(a)
配線基板の表面に、第1接着フィルムを介して第1電子部品を仮設置する工程;
工程(b)
配線基板の裏面に、第1接着フィルムの硬化温度よりも低い硬化温度を有する第2接着フィルムを介して第2電子部品を仮設置する工程;
工程(c)
第1電子部品及び第2電子部品が仮設置された配線基板を、圧着受け台に載置する工程;及び
工程(d)
第1電子部品を、配線基板に対して第1電子部品側から加熱加圧ツールで押圧しながら、第1接着フィルムがその硬化温度に到達するように、第2接着フィルムがその硬化温度に到達するように且つ第1接着フィルムが加熱により到達する到達温度が第2接着フィルムが加熱により到達する到達温度よりも高くなるように、加熱することにより、配線基板の表面及び裏面に第1電子部品及び第2電子部品をそれぞれ一括で実装する工程
を有することを特徴とする製造方法。 - 第1接着フィルムの硬化温度が200〜250℃であり、第2接着フィルムの硬化温度が170〜220℃である請求項1記載の製造方法。
- 加熱加圧ツールの押圧面が弾性材料から形成されている請求項1または2に記載の製造方法。
- 第1電子部品及び第2電子部品が仮設置された配線基板が、第2電子部品側から載置される圧着受け台の配線基板載置面が、弾性材料から形成されている請求項3記載の製造方法。
- 工程(d)において、第1電子部品を、配線基板に対して第1電子部品側から加熱加圧ツールで押圧しながら加熱する際に、第1電子部品及び第2電子部品が仮設置された配線基板の両面に保護シートを配置させて押圧する請求項1〜4のいずれかに記載の製造方法。
- 第1電子部品及び第2電子部品の少なくともいずれか一方が半導体チップである請求項1〜5のいずれかに記載の製造方法。
- 第1電子部品及び第2電子部品の少なくともいずれか一方が、シリコン貫通電極とそれに接続しているフロントバンプとバックバンプとを有し、互いに積層されるべき複数の半導体チップであり、半導体チップ間に存在するフロントバンプ及びバックバンプのいずれかの少なくとも一部がハンダで形成されている請求項1記載の製造方法。
- 請求項1〜7の製造方法により製造された接続構造体。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011098967A JP5741188B2 (ja) | 2011-04-27 | 2011-04-27 | 接続構造体の製造方法 |
US14/112,277 US9318353B2 (en) | 2011-04-27 | 2012-04-02 | Method of manufacturing connection structure |
PCT/JP2012/058889 WO2012147458A1 (ja) | 2011-04-27 | 2012-04-02 | 接続構造体の製造方法 |
KR1020137027942A KR101858783B1 (ko) | 2011-04-27 | 2012-04-02 | 접속 구조체의 제조 방법 |
TW101113431A TWI494038B (zh) | 2011-04-27 | 2012-04-16 | Method of manufacturing a connecting structure |
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JP2011098967A JP5741188B2 (ja) | 2011-04-27 | 2011-04-27 | 接続構造体の製造方法 |
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JP2012231039A JP2012231039A (ja) | 2012-11-22 |
JP5741188B2 true JP5741188B2 (ja) | 2015-07-01 |
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US (1) | US9318353B2 (ja) |
JP (1) | JP5741188B2 (ja) |
KR (1) | KR101858783B1 (ja) |
TW (1) | TWI494038B (ja) |
WO (1) | WO2012147458A1 (ja) |
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JP5819026B1 (ja) * | 2014-02-24 | 2015-11-18 | 積水化学工業株式会社 | 接続構造体の製造方法 |
JP2016162985A (ja) | 2015-03-05 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6271463B2 (ja) * | 2015-03-11 | 2018-01-31 | 東芝メモリ株式会社 | 半導体装置 |
KR102322766B1 (ko) | 2015-09-03 | 2021-11-08 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS5376372A (en) * | 1976-12-17 | 1978-07-06 | Matsushita Electric Ind Co Ltd | Device for attaching chip circuit parts |
DE3104623A1 (de) * | 1981-02-10 | 1982-08-26 | Robert Bosch Gmbh, 7000 Stuttgart | Verfahren zum befestigen von bauelementen mit flaechigen anschlusskontakten und bauelement hierfuer |
US4761881A (en) * | 1986-09-15 | 1988-08-09 | International Business Machines Corporation | Single step solder process |
US5155904A (en) * | 1991-04-03 | 1992-10-20 | Compaq Computer Corporation | Reflow and wave soldering techniques for bottom side components |
US5678304A (en) * | 1996-07-24 | 1997-10-21 | Eastman Kodak Company | Method for manufacturing double-sided circuit assemblies |
JP3853979B2 (ja) * | 1998-06-16 | 2006-12-06 | 日東電工株式会社 | 半導体装置の製法 |
JP3300698B2 (ja) * | 2000-05-17 | 2002-07-08 | 松下電器産業株式会社 | 半導体実装対象中間構造体及び半導体装置の製造方法 |
JP2001332682A (ja) * | 2000-05-19 | 2001-11-30 | Matsushita Electric Ind Co Ltd | 半導体素子実装方法および半導体素子実装構造 |
JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP2006229106A (ja) * | 2005-02-21 | 2006-08-31 | Matsushita Electric Ind Co Ltd | 半導体装置の実装方法と実装装置および半導体装置 |
JP4832107B2 (ja) | 2006-02-23 | 2011-12-07 | ソニーケミカル&インフォメーションデバイス株式会社 | 実装方法 |
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