JP5704844B2 - バイポーラ・トランジスタ構造およびその製造方法 - Google Patents

バイポーラ・トランジスタ構造およびその製造方法 Download PDF

Info

Publication number
JP5704844B2
JP5704844B2 JP2010141326A JP2010141326A JP5704844B2 JP 5704844 B2 JP5704844 B2 JP 5704844B2 JP 2010141326 A JP2010141326 A JP 2010141326A JP 2010141326 A JP2010141326 A JP 2010141326A JP 5704844 B2 JP5704844 B2 JP 5704844B2
Authority
JP
Japan
Prior art keywords
region
layer
emitter
impurity
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010141326A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011003907A5 (enExample
JP2011003907A (ja
Inventor
アンソニー・ケイ・スタンパー
エリック・マティアス・ダールストローム
ジョン・ジョセフ・ブノワ
ピーター・ブライアン・グレイ
マーク・デイビッド・デュピュイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2011003907A publication Critical patent/JP2011003907A/ja
Publication of JP2011003907A5 publication Critical patent/JP2011003907A5/ja
Application granted granted Critical
Publication of JP5704844B2 publication Critical patent/JP5704844B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H10D62/864—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H10D62/138—Pedestal collectors

Landscapes

  • Bipolar Transistors (AREA)
JP2010141326A 2009-06-22 2010-06-22 バイポーラ・トランジスタ構造およびその製造方法 Expired - Fee Related JP5704844B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/488899 2009-06-22
US12/488,899 US8482101B2 (en) 2009-06-22 2009-06-22 Bipolar transistor structure and method including emitter-base interface impurity

Publications (3)

Publication Number Publication Date
JP2011003907A JP2011003907A (ja) 2011-01-06
JP2011003907A5 JP2011003907A5 (enExample) 2014-07-31
JP5704844B2 true JP5704844B2 (ja) 2015-04-22

Family

ID=43353532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010141326A Expired - Fee Related JP5704844B2 (ja) 2009-06-22 2010-06-22 バイポーラ・トランジスタ構造およびその製造方法

Country Status (4)

Country Link
US (1) US8482101B2 (enExample)
JP (1) JP5704844B2 (enExample)
KR (1) KR20100137356A (enExample)
CN (1) CN101930998A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761701B2 (en) 2014-05-01 2017-09-12 Infineon Technologies Ag Bipolar transistor
US10916642B2 (en) 2019-04-18 2021-02-09 Globalfoundries U.S. Inc. Heterojunction bipolar transistor with emitter base junction oxide interface
US11862717B2 (en) 2021-08-24 2024-01-02 Globalfoundries U.S. Inc. Lateral bipolar transistor structure with superlattice layer and method to form same
US20230352570A1 (en) * 2022-04-29 2023-11-02 Globalfoundries U.S. Inc. Bipolar junction transistor

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815303B2 (en) 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
GB9907184D0 (en) * 1999-03-30 1999-05-26 Philips Electronics Nv A method of manufacturing a semiconductor device
FR2805923B1 (fr) * 2000-03-06 2002-05-24 St Microelectronics Sa Procede de fabrication d'un transistor bipolaire double- polysilicium auto-aligne
JP3528756B2 (ja) 2000-05-12 2004-05-24 松下電器産業株式会社 半導体装置
US6541346B2 (en) 2001-03-20 2003-04-01 Roger J. Malik Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process
US20050250289A1 (en) 2002-10-30 2005-11-10 Babcock Jeffrey A Control of dopant diffusion from buried layers in bipolar integrated circuits
US6794237B2 (en) * 2001-12-27 2004-09-21 Texas Instruments Incorporated Lateral heterojunction bipolar transistor
US6670654B2 (en) 2002-01-09 2003-12-30 International Business Machines Corporation Silicon germanium heterojunction bipolar transistor with carbon incorporation
US6858532B2 (en) * 2002-12-10 2005-02-22 International Business Machines Corporation Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
JP2004228605A (ja) * 2004-05-14 2004-08-12 Matsushita Electric Ind Co Ltd エッチング方法
JP2006324294A (ja) * 2005-05-17 2006-11-30 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7300849B2 (en) * 2005-11-04 2007-11-27 Atmel Corporation Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement
US7651919B2 (en) * 2005-11-04 2010-01-26 Atmel Corporation Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization
US7601629B2 (en) * 2005-12-20 2009-10-13 Texas Instruments Incorporated Semiconductive device fabricated using subliming materials to form interlevel dielectrics
US7812339B2 (en) * 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures

Also Published As

Publication number Publication date
CN101930998A (zh) 2010-12-29
US20100320571A1 (en) 2010-12-23
US8482101B2 (en) 2013-07-09
KR20100137356A (ko) 2010-12-30
JP2011003907A (ja) 2011-01-06

Similar Documents

Publication Publication Date Title
US8525293B2 (en) Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration
US8785281B2 (en) CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials
US8828812B2 (en) Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof
JP5704844B2 (ja) バイポーラ・トランジスタ構造およびその製造方法
US20090227100A1 (en) Method for fabricating semiconductor device
US8133791B2 (en) Method of manufacturing a bipolar transistor and bipolar transistor obtained therewith
JP2009526396A (ja) バイポーラトランジスタの製造方法
JP3321553B2 (ja) Ｂｉ−ＣＭＯＳ集積回路装置の製造方法
US9209264B2 (en) Heterojunction bipolar transistor having a germanium raised extrinsic base
JPH10326793A (ja) 半導体装置の製造方法
TWI272651B (en) Method for fabricating semiconductor device
CN104637879A (zh) 一种半导体器件的制备方法
JP4745187B2 (ja) 半導体装置の製造方法
US7645666B2 (en) Method of making a semiconductor device
JP2005026707A (ja) 半導体装置及びその製造方法
CN101236990A (zh) 半导体结构及其制造方法
US20160043202A1 (en) Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures
JP4458895B2 (ja) バイポーラトランジスタ
US20030219963A1 (en) Self-aligned method for fabricating epitaxial base bipolar transistor device
JP5034267B2 (ja) 半導体装置の製造方法
JP2005167125A (ja) 半導体装置及びその製造方法
JPH06188252A (ja) バイポーラトランジスタの製造方法
JPH0621071A (ja) 半導体装置の製造方法
JP2006128334A (ja) バイポーラトランジスタの製造方法及びバイポーラトランジスタを有する半導体装置の製造方法
JP2005203460A (ja) 半導体装置の製造方法及び半導体装置、並びにバイポーラトランジスタの製造方法及びバイポーラトランジスタ

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130301

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140530

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20140530

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20140530

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20140530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20140603

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20140624

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140714

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20140716

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140716

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20141014

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20141015

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141015

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20150114

TRDD Decision of grant or rejection written
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20150202

RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20150202

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150202

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150224

R150 Certificate of patent or registration of utility model

Ref document number: 5704844

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees