JP5676833B2 - 電気めっきを使用して形成される集積回路パッケージを処理するための方法およびそれから作成された装置 - Google Patents
電気めっきを使用して形成される集積回路パッケージを処理するための方法およびそれから作成された装置 Download PDFInfo
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- JP5676833B2 JP5676833B2 JP2005188120A JP2005188120A JP5676833B2 JP 5676833 B2 JP5676833 B2 JP 5676833B2 JP 2005188120 A JP2005188120 A JP 2005188120A JP 2005188120 A JP2005188120 A JP 2005188120A JP 5676833 B2 JP5676833 B2 JP 5676833B2
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- 238000009713 electroplating Methods 0.000 title claims description 63
- 238000000034 method Methods 0.000 title claims description 47
- 238000007747 plating Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 28
- 229910052802 copper Inorganic materials 0.000 description 26
- 239000010949 copper Substances 0.000 description 26
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 2
- ZEMPKEQAKRGZGQ-AAKVHIHISA-N 2,3-bis[[(z)-12-hydroxyoctadec-9-enoyl]oxy]propyl (z)-12-hydroxyoctadec-9-enoate Chemical compound CCCCCCC(O)C\C=C/CCCCCCCC(=O)OCC(OC(=O)CCCCCCC\C=C/CC(O)CCCCCC)COC(=O)CCCCCCC\C=C/CC(O)CCCCCC ZEMPKEQAKRGZGQ-AAKVHIHISA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
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Description
上述の通り、従来の処理では、キャビティ・ダウン・パッケージのような集積回路パッケージにニッケルおよび金を電気めっきするには、電気めっき中に使用される電流をめっきされる露出パッド領域に通すために、接続を実現するためのめっきトレースが必要である。電気めっき後に、集積回路パッケージに存在し、約2GHzを超える周波数で動作する集積回路の電気的性能を向上するために、めっきトレースはエッチングによって除去される。触られていないままのめっきトレースはアンテナとして働き、集積回路パッケージ内にパッケージされたICの機能エラーを引き起こすおそれがある。しかし、めっきトレースを除去するプロセスさえも、下述するように問題を引き起こす。
本発明の例示的実施形態は、集積回路パッケージのパッド側100にめっきテール110を持たない方法およびそれにより作られた装置を提供することによって、上記の問題を解決する。
Claims (7)
- 集積回路パッケージを処理するための方法であって、
前記集積回路パッケージのバック・プレーンを1つ又は複数の電流源に電気的に結合する工程と、
集積回路パッケージのパッド側の導電性表面にめっきトレースを形成しないように集積回路パッケージを電気めっきする工程を含み、前記電気めっきの工程により前記集積回路パッケージの複数のパッド領域に1つまたは複数の材料をめっきし、前記電気的に結合する工程は、前記電気めっきの工程前に実行され、前記電気めっき工程の前にエッチングにより金属層の少なくとも一部を取り除き、電気的結合が前記電気めっきの工程の少なくとも一部分の間に維持され、前記電気的に結合する工程は、前記電気めっきの工程を促進するために1つ又は複数のスルーホールと前記バック・プレーンを介して電流を流す、集積回路パッケージを処理するための方法。 - 前記集積回路パッケージの前記パッド領域の1つまたは複数に集積回路を結合する工程をさらに含む、請求項1に記載の方法。
- 前記集積回路パッケージのバック・プレーンをパターン形成する工程をさらに含み、前記パターン形成の工程が前記電気めっきの工程後に行なわれる、請求項1に記載の方法。
- 前記集積回路パッケージがパネル内の複数の集積回路パッケージの1つであり、
前記電気めっきの工程が、前記集積回路パッケージのパッド側の導電性表面にめっきトレースを形成しないように前記集積回路パッケージの各々を電気めっきする工程をさらに含み、前記電気めっきの工程により前記集積回路パッケージの複数のパッド領域に1つまたは複数の材料をめっきする、請求項1に記載の方法。 - 前記バック・プレーンを電気めっきする前記工程を実行するときに、前記バック・プレーンが実質的にパターン形成されていない、請求項3に記載の方法。
- 集積回路をパッケージするための集積回路パッケージであって、
前記集積回路パッケージは、
前記集積回路パッケージのバック・プレーンを1つ又は複数の電流源に電気的に結合する工程と、
前記集積回路パッケージのパッド側の導電性表面にめっきトレースを形成しないように前記集積回路パッケージを電気めっきする工程であって、前記集積回路パッケージの複数のパッド領域に1つまたは複数の材料をめっきする工程を含むプロセスによって作成され、
前記電気的に結合する工程は、前記電気めっきの工程前に実行され、前記電気めっき工程の前にエッチングにより金属層の少なくとも一部を取り除き、電気的結合が前記電気めっきの工程の少なくとも一部分の間に維持され、前記電気的に結合する工程は、前記電気めっきの工程を促進するために1つ又は複数のスルーホールと前記バック・プレーンを介して電流を流すことを特徴とする、集積回路パッケージ。 - 前記プロセスが集積回路パッケージのバック・プレーンをパターン形成する工程をさらに含み、前記パターン形成の工程が前記電気めっきの工程後に行なわれる、請求項6に記載の集積回路パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/878,157 US7157361B2 (en) | 2004-06-28 | 2004-06-28 | Methods for processing integrated circuit packages formed using electroplating and apparatus made therefrom |
US10/878157 | 2004-06-28 |
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JP2006013519A JP2006013519A (ja) | 2006-01-12 |
JP5676833B2 true JP5676833B2 (ja) | 2015-02-25 |
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JP6152254B2 (ja) * | 2012-09-12 | 2017-06-21 | 新光電気工業株式会社 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
KR20140108865A (ko) * | 2013-03-04 | 2014-09-15 | 삼성전자주식회사 | 패키지 기판, 패키지 기판의 제조 방법 및 패키지 기판을 포함하는 반도체 패키지 |
CN111246669B (zh) * | 2020-01-17 | 2021-07-30 | 深圳市德明利技术股份有限公司 | 一种lpddr基板设计方法、lpddr基板和电子设备 |
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JP3339473B2 (ja) * | 1999-08-26 | 2002-10-28 | 日本電気株式会社 | パッケージ基板、該パッケージ基板を備える半導体装置及びそれらの製造方法 |
JP2001068828A (ja) * | 1999-08-27 | 2001-03-16 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
TW445558B (en) * | 2000-04-14 | 2001-07-11 | Via Tech Inc | Manufacturing method for cavity-down plastic ball grid array package substrate |
US6569712B2 (en) * | 2001-10-19 | 2003-05-27 | Via Technologies, Inc. | Structure of a ball-grid array package substrate and processes for producing thereof |
-
2004
- 2004-06-28 US US10/878,157 patent/US7157361B2/en active Active
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2005
- 2005-06-27 KR KR1020050055694A patent/KR101421714B1/ko active IP Right Grant
- 2005-06-28 JP JP2005188120A patent/JP5676833B2/ja active Active
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US7157361B2 (en) | 2007-01-02 |
KR101421714B1 (ko) | 2014-08-13 |
JP2006013519A (ja) | 2006-01-12 |
US20060014370A1 (en) | 2006-01-19 |
KR20060048554A (ko) | 2006-05-18 |
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