JP5643896B2 - デイジーチェーン接続されたデバイスのための高速インターフェイス - Google Patents

デイジーチェーン接続されたデバイスのための高速インターフェイス Download PDF

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Publication number
JP5643896B2
JP5643896B2 JP2013512704A JP2013512704A JP5643896B2 JP 5643896 B2 JP5643896 B2 JP 5643896B2 JP 2013512704 A JP2013512704 A JP 2013512704A JP 2013512704 A JP2013512704 A JP 2013512704A JP 5643896 B2 JP5643896 B2 JP 5643896B2
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Japan
Prior art keywords
command
port
memory device
data
memory
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JP2013512704A
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Japanese (ja)
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JP2013527541A (ja
JP2013527541A5 (https=
Inventor
ビョン ジン チョイ
ビョン ジン チョイ
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Mosaid Technologies Inc
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Conversant Intellectual Property Management Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Information Transfer Systems (AREA)
JP2013512704A 2010-05-31 2011-05-31 デイジーチェーン接続されたデバイスのための高速インターフェイス Expired - Fee Related JP5643896B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US34994310P 2010-05-31 2010-05-31
US61/349,943 2010-05-31
US13/012,754 US8463959B2 (en) 2010-05-31 2011-01-24 High-speed interface for daisy-chained devices
US13/012,754 2011-01-24
PCT/CA2011/000614 WO2011150496A1 (en) 2010-05-31 2011-05-31 High speed interface for daisy-chained devices

Publications (3)

Publication Number Publication Date
JP2013527541A JP2013527541A (ja) 2013-06-27
JP2013527541A5 JP2013527541A5 (https=) 2014-03-20
JP5643896B2 true JP5643896B2 (ja) 2014-12-17

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JP2013512704A Expired - Fee Related JP5643896B2 (ja) 2010-05-31 2011-05-31 デイジーチェーン接続されたデバイスのための高速インターフェイス

Country Status (7)

Country Link
US (2) US8463959B2 (https=)
EP (1) EP2577473A4 (https=)
JP (1) JP5643896B2 (https=)
KR (1) KR20130085956A (https=)
CN (1) CN102947806A (https=)
CA (1) CA2801153A1 (https=)
WO (1) WO2011150496A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150102943A1 (en) * 2013-10-10 2015-04-16 Datang Nxp Semiconductors Co., Ltd. Daisy-chain communication bus and protocol
EP3018544B1 (de) * 2014-11-07 2018-02-21 Siemens Aktiengesellschaft Produktions- oder Werkzeugmaschine und Verfahren zum Betrieb einer Produktions- oder Werkzeugmaschine
US10270655B2 (en) * 2015-01-29 2019-04-23 Robert Bosch Gmbh Method for running a computer network and computer network
KR102648180B1 (ko) * 2016-07-19 2024-03-18 에스케이하이닉스 주식회사 메모리 시스템 및 그 동작 방법
JP2019057344A (ja) 2017-09-20 2019-04-11 東芝メモリ株式会社 メモリシステム

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6799235B2 (en) 2002-01-02 2004-09-28 Intel Corporation Daisy chain latency reduction
JP4104939B2 (ja) * 2002-08-29 2008-06-18 新日本無線株式会社 マルチプロセッサシステム
US20060041715A1 (en) * 2004-05-28 2006-02-23 Chrysos George Z Multiprocessor chip having bidirectional ring interconnect
US7254663B2 (en) 2004-07-22 2007-08-07 International Business Machines Corporation Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems
JP2006065697A (ja) * 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
US7334070B2 (en) 2004-10-29 2008-02-19 International Business Machines Corporation Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels
KR100666225B1 (ko) 2005-02-17 2007-01-09 삼성전자주식회사 데이지 체인을 형성하는 멀티 디바이스 시스템 및 이의 구동방법
EP1932158A4 (en) 2005-09-30 2008-10-15 Mosaid Technologies Inc MEMORY WITH OUTPUT CONTROL
US20070076502A1 (en) * 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US20070165457A1 (en) * 2005-09-30 2007-07-19 Jin-Ki Kim Nonvolatile memory system
US7620763B2 (en) * 2006-07-26 2009-11-17 International Business Machines Corporation Memory chip having an apportionable data bus
US7342816B2 (en) 2006-07-26 2008-03-11 International Business Machines Corporation Daisy chainable memory chip
US7673093B2 (en) 2006-07-26 2010-03-02 International Business Machines Corporation Computer system having daisy chained memory chips
US7545664B2 (en) 2006-07-26 2009-06-09 International Business Machines Corporation Memory system having self timed daisy chained memory chips
US7345900B2 (en) 2006-07-26 2008-03-18 International Business Machines Corporation Daisy chained memory system
US7577811B2 (en) * 2006-07-26 2009-08-18 International Business Machines Corporation Memory controller for daisy chained self timed memory chips
US7966469B2 (en) * 2006-08-14 2011-06-21 Qimonda Ag Memory system and method for operating a memory system
WO2008067650A1 (en) * 2006-12-06 2008-06-12 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US7925854B2 (en) * 2006-12-06 2011-04-12 Mosaid Technologies Incorporated System and method of operating memory devices of mixed type
JP5683813B2 (ja) * 2006-12-06 2015-03-11 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドＣｏｎｖｅｒｓａｎｔ Ｉｎｔｅｌｌｅｃｔｕａｌ Ｐｒｏｐｅｒｔｙ Ｍａｎａｇｅｍｅｎｔ Ｉｎｃ． 混合されたタイプのメモリデバイスを動作させるシステムおよび方法
US7650459B2 (en) 2006-12-21 2010-01-19 Intel Corporation High speed interface for non-volatile memory
KR101494065B1 (ko) * 2007-02-16 2015-02-23 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드 반도체 장치 및 상호접속된 장치들을 갖는 시스템에서의 전력 소비를 감소시키는 방법
US8046527B2 (en) * 2007-02-22 2011-10-25 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
EP2132635B1 (en) * 2007-03-30 2017-08-16 Rambus Inc. System including hierarchical memory modules having different types of integrated circuit memory devices
US7688652B2 (en) 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
US20090063786A1 (en) * 2007-08-29 2009-03-05 Hakjune Oh Daisy-chain memory configuration and usage
US8095747B2 (en) * 2008-09-26 2012-01-10 Cypress Semiconductor Corporation Memory system and method

Also Published As

Publication number Publication date
JP2013527541A (ja) 2013-06-27
EP2577473A4 (en) 2015-02-11
CA2801153A1 (en) 2011-12-08
EP2577473A1 (en) 2013-04-10
KR20130085956A (ko) 2013-07-30
US8463959B2 (en) 2013-06-11
US20110296056A1 (en) 2011-12-01
US20130275628A1 (en) 2013-10-17
WO2011150496A1 (en) 2011-12-08
CN102947806A (zh) 2013-02-27

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