JP5639749B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

Info

Publication number
JP5639749B2
JP5639749B2 JP2009134374A JP2009134374A JP5639749B2 JP 5639749 B2 JP5639749 B2 JP 5639749B2 JP 2009134374 A JP2009134374 A JP 2009134374A JP 2009134374 A JP2009134374 A JP 2009134374A JP 5639749 B2 JP5639749 B2 JP 5639749B2
Authority
JP
Japan
Prior art keywords
layer
resin
wiring
insulating
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009134374A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010021534A5 (enExample
JP2010021534A (ja
Inventor
章裕 千田
章裕 千田
青木　智幸
智幸 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2009134374A priority Critical patent/JP5639749B2/ja
Publication of JP2010021534A publication Critical patent/JP2010021534A/ja
Publication of JP2010021534A5 publication Critical patent/JP2010021534A5/ja
Application granted granted Critical
Publication of JP5639749B2 publication Critical patent/JP5639749B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/029—Woven fibrous reinforcement or textile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1147—Sealing or impregnating, e.g. of pores
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/257—Arrangements for cooling characterised by their materials having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh or porous structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T442/00—Fabric [woven, knitted, or nonwoven textile or cloth, etc.]
    • Y10T442/20—Coated or impregnated woven, knit, or nonwoven fabric which is not [a] associated with another preformed layer or fiber layer or, [b] with respect to woven and knit, characterized, respectively, by a particular or differential weave or knit, wherein the coating or impregnation is neither a foamed material nor a free metal or alloy layer
    • Y10T442/2418—Coating or impregnation increases electrical conductivity or anti-static quality

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Non-Volatile Memory (AREA)
JP2009134374A 2008-06-10 2009-06-03 半導体装置の作製方法 Expired - Fee Related JP5639749B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009134374A JP5639749B2 (ja) 2008-06-10 2009-06-03 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008151227 2008-06-10
JP2008151227 2008-06-10
JP2009134374A JP5639749B2 (ja) 2008-06-10 2009-06-03 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2010021534A JP2010021534A (ja) 2010-01-28
JP2010021534A5 JP2010021534A5 (enExample) 2012-07-12
JP5639749B2 true JP5639749B2 (ja) 2014-12-10

Family

ID=41399564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009134374A Expired - Fee Related JP5639749B2 (ja) 2008-06-10 2009-06-03 半導体装置の作製方法

Country Status (3)

Country Link
US (1) US8044499B2 (enExample)
JP (1) JP5639749B2 (enExample)
KR (1) KR101594316B1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009148001A1 (en) * 2008-06-06 2009-12-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP2010041045A (ja) 2008-07-09 2010-02-18 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
WO2010032611A1 (en) 2008-09-19 2010-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5583951B2 (ja) * 2008-11-11 2014-09-03 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI517268B (zh) * 2009-08-07 2016-01-11 半導體能源研究所股份有限公司 端子構造的製造方法和電子裝置的製造方法
US8345435B2 (en) * 2009-08-07 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Terminal structure and manufacturing method thereof, and electronic device and manufacturing method thereof
JP5719560B2 (ja) * 2009-10-21 2015-05-20 株式会社半導体エネルギー研究所 端子構造の作製方法
TWI473551B (zh) * 2011-07-08 2015-02-11 欣興電子股份有限公司 封裝基板及其製法
JP2013115083A (ja) * 2011-11-25 2013-06-10 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
HUE029702T2 (en) * 2013-10-17 2017-03-28 Das Energy Gmbh Photovoltaic panel and method for its production
US20150122532A1 (en) * 2013-11-04 2015-05-07 Teledyne Technologies Incorporated High temperature multilayer flexible printed wiring board
JP5898391B1 (ja) * 2014-07-28 2016-04-06 東邦テナックス株式会社 プリプレグおよび繊維強化複合材料
CN108235600B (zh) * 2017-12-28 2019-07-12 广州兴森快捷电路科技有限公司 印刷线路板的制备方法
CN121152127B (zh) * 2025-11-18 2026-03-27 深圳市卡博尔科技有限公司 一种高密度互联电路板及其制备方法
CN121262719B (zh) * 2025-12-04 2026-03-27 深圳市卡博尔科技有限公司 一种柔性线路板对接结构及其对接方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60200590A (ja) * 1984-03-24 1985-10-11 ダイソー株式会社 印刷回路基板及びその製法
JPH06200590A (ja) * 1992-12-29 1994-07-19 Sekisui House Ltd 間仕切パネル
JP3402400B2 (ja) * 1994-04-22 2003-05-06 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JPH1092980A (ja) 1996-09-13 1998-04-10 Toshiba Corp 無線カードおよびその製造方法
JPH10256687A (ja) * 1997-03-14 1998-09-25 Matsushita Electric Ind Co Ltd ビアホール充填用導体ペースト組成物とそれを用いたプリント配線基板
US6224965B1 (en) 1999-06-25 2001-05-01 Honeywell International Inc. Microfiber dielectrics which facilitate laser via drilling
JP2001024081A (ja) * 1999-07-08 2001-01-26 Toshiba Corp 導電基体及びその製造方法
JP4423779B2 (ja) 1999-10-13 2010-03-03 味の素株式会社 エポキシ樹脂組成物並びに該組成物を用いた接着フィルム及びプリプレグ、及びこれらを用いた多層プリント配線板及びその製造法
US8415208B2 (en) 2001-07-16 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US6903377B2 (en) 2001-11-09 2005-06-07 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method for manufacturing the same
KR100430001B1 (ko) 2001-12-18 2004-05-03 엘지전자 주식회사 다층기판의 제조방법, 그 다층기판의 패드 형성방법 및 그다층기판을 이용한 반도체 패키지의 제조방법
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
EP1514307A1 (en) 2002-06-19 2005-03-16 Sten Bjorsell Electronics circuit manufacture
WO2004064467A1 (ja) * 2003-01-16 2004-07-29 Fujitsu Limited 多層配線基板、その製造方法、および、ファイバ強化樹脂基板の製造方法
JP4540359B2 (ja) 2004-02-10 2010-09-08 シャープ株式会社 半導体装置およびその製造方法
EP1589797A3 (en) 2004-04-19 2008-07-30 Matsushita Electric Industrial Co., Ltd. Manufacturing method of laminated substrate, and manufacturing apparatus of semiconductor device for module and laminated substrate for use therein
KR101226260B1 (ko) 2004-06-02 2013-01-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 제조방법
JP4693619B2 (ja) * 2004-12-17 2011-06-01 株式会社半導体エネルギー研究所 導電層を有する基板の作製方法及び半導体装置の作製方法
JP2007091822A (ja) 2005-09-27 2007-04-12 Shin Kobe Electric Mach Co Ltd プリプレグ
US8212953B2 (en) 2005-12-26 2012-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5296360B2 (ja) 2006-10-04 2013-09-25 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
EP2067173A4 (en) 2006-10-04 2015-03-18 Semiconductor Energy Lab SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR
EP1970951A3 (en) 2007-03-13 2009-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
EP1976001A3 (en) 2007-03-26 2012-08-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR101582503B1 (ko) 2008-05-12 2016-01-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
JP5473413B2 (ja) 2008-06-20 2014-04-16 株式会社半導体エネルギー研究所 配線基板の作製方法、アンテナの作製方法及び半導体装置の作製方法

Also Published As

Publication number Publication date
US20090302457A1 (en) 2009-12-10
US8044499B2 (en) 2011-10-25
KR101594316B1 (ko) 2016-02-16
JP2010021534A (ja) 2010-01-28
KR20090128336A (ko) 2009-12-15

Similar Documents

Publication Publication Date Title
JP5473413B2 (ja) 配線基板の作製方法、アンテナの作製方法及び半導体装置の作製方法
JP5663687B2 (ja) 半導体装置の作製方法
KR101594316B1 (ko) 배선기판 및 그 제작방법, 및 반도체장치 및 그 제작방법
JP6461227B2 (ja) 半導体装置
JP2008270761A (ja) 半導体装置の作製方法
JP2009081426A (ja) 半導体装置の作製方法
JP2007241999A (ja) 半導体装置
JP5583951B2 (ja) 半導体装置の作製方法
JP4912900B2 (ja) 半導体装置の作製方法
JP2010027818A (ja) 配線基板及びその作製方法、並びに、半導体装置及びその作製方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120529

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130530

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130604

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130624

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130920

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20131108

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20131220

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140808

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141027

R150 Certificate of patent or registration of utility model

Ref document number: 5639749

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees