JP5587144B2 - スイッチマトリクスモジュールを備えたクロスポイントスイッチ - Google Patents
スイッチマトリクスモジュールを備えたクロスポイントスイッチ Download PDFInfo
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- JP5587144B2 JP5587144B2 JP2010255280A JP2010255280A JP5587144B2 JP 5587144 B2 JP5587144 B2 JP 5587144B2 JP 2010255280 A JP2010255280 A JP 2010255280A JP 2010255280 A JP2010255280 A JP 2010255280A JP 5587144 B2 JP5587144 B2 JP 5587144B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/65—Re-configuration of fast packet switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Networks & Wireless Communication (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Description
103 スイッチ構成レジスタ
105 ステージングレジスタ
107 ユーザ初期化レジスタ
109 プログラミングインタフェース
111 一次アクセスポート
113 2次アクセスポート
201 入力信号等化回路
203 出力レベル制御回路
301 入力バス
303 出力バス
Claims (17)
- スイッチマトリクスモジュールを備えたクロスポイントスイッチユニットにおいて、
前記スイッチマトリクスモジュールであって、
複数のアクティブエレメントを備えた半導体基板を含む第1のエレメントと、
前記第1のエレメントに結合され、前記スイッチマトリクスモジュールの入力に結合された第1の伝送ラインの組みと、前記スイッチマトリクスモジュールの出力に結合された第2の伝送ラインの組みを含み、前記第2の伝送ラインの組みは前記第1の伝送ラインの組みに直交する第2のエレメントと、
前記第1の伝送ラインの組の複数の伝送ラインに接続されたパッシブネットワークであって、前記第1の伝送ラインの以前で信号の劣化を補償する容量及び抵抗を備え、かつ、前記スイッチマトリクスモジュールとして集積回路の同じダイ上に埋め込まれたパッシブネットワークと、を備える、前記スイッチマトリクスモジュールと、および
クロスポイントスイッチと、を備え、
前記クロスポイントスイッチは前記複数のアクティブエレメントに結合された複数のプログラマブルレジスタを備え、
前記複数のアクティブエレメントの各アクティブエレメントは、タップを介して、前記第1の伝送ラインの組みの1つの伝送ラインと前記第2の伝送ラインの1つの伝送ラインと結合される、
クロスポイントスイッチユニット。 - 前記タップはバイアホールである請求項1に記載のクロスポイントスイッチユニット。
- 前記第2のエレメントに結合された二次基板をさらに具備する請求項1に記載のクロスポイントスイッチユニット。
- 前記入力及び出力は、ボールグリッドアレイを介して印刷回路基板のパッドに結合される請求項1に記載のクロスポイントスイッチユニット。
- 入力及び出力を含む第2のスイッチマトリクスモジュールをさらに備え、前記第2のスイッチマトリクスモジュールの前記入力は前記スイッチマトリクスモジュールの出力に結合される請求項1に記載のクロスポイントスイッチユニット。
- 前記パッシブネットワークの前記抵抗と容量は、ラインを結合する抵抗を備えた差動信号の各ライン上に並列に設けられている請求項1に記載のクロスポイントスイッチユニット。
- 前記パッシブネットワークは、高い周波数での信号減衰を減少させる請求項1に記載のクロスポイントスイッチユニット。
- 前記クロスポイントスイッチは、スイッチコアに結合されたプログラミングインタフェースと、前記プログラミングインタフェースによる命令によって、前記スイッチマトリクスモジュールの出力の出力駆動レベルを設定するスイッチ構成レジスタと、をさらに具備する請求項1に記載のクロスポイントスイッチユニット。
- 前記クロスポイントスイッチは、スイッチコアに結合されたプログラミングインタフェースをさらに具備する請求項1に記載のクロスポイントスイッチユニット。
- 前記プログラミングインタフェースに結合され前記プログラミングインタフェースに命令を与える1次アクセスポートと、前記プログラミングインタフェースに結合され前記1次アクセスポートの使用中に利用される2次アクセスポートと、をさらに具備する請求項9に記載のクロスポイントスイッチユニット。
- 前記スイッチマトリクスモジュールに結合され前記プログラミングインタフェースにより提供されるプログラミングデータを格納するユーザレジスタをさらに備え、前記プログラミングデータは、ユーザにより特定され、前記スイッチマトリクスモジュールの入力から出力の相互接続に関連したマップ情報を含む請求項9に記載のクロスポイントスイッチユニット。
- 前記スイッチコアに結合されたステージレジスタをさらに備え、前記プログラミングインタフェースは、前記ステージレジスタに予め格納されたプログラミングデータを格納し、後刻に前記ステージレジスタに前記プログラミングデータを与える請求項9に記載のクロスポイントスイッチユニット。
- 前記プログラミングインタフェースは、前記プログラミングインタフェースにより特定され連続的に出力から入力への一連の関係したプログラミングデータを提供する形態である請求項9に記載のクロスポイントスイッチユニット。
- 前記プログラミングインタフェースは、前記スイッチマトリクスモジュールの入力及び出力のグループの形態をとる請求項9に記載のクロスポイントスイッチユニット。
- 前記プログラミングインタフェースは、入力のグループから出力のグループに一連に関連している請求項12に記載のクロスポイントスイッチユニット。
- 前記入力及び出力は、入力及び出力の数字の順番に基づいてグループ分けされる請求項13に記載のクロスポイントスイッチユニット。
- 前記入力及び出力は、前記スイッチコアに関連した前記入力及び出力の場所に基づいてグループ分けされる請求項14に記載のクロスポイントスイッチユニット。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US20955200P | 2000-06-06 | 2000-06-06 | |
US60/209,552 | 2000-06-06 | ||
US22755000P | 2000-08-23 | 2000-08-23 | |
US60/227,550 | 2000-08-23 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2002502605A Division JP2003536300A (ja) | 2000-06-06 | 2001-06-06 | スイッチマトリクスモジュールを備えたクロスポイントスイッチ |
Publications (2)
Publication Number | Publication Date |
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JP2011045136A JP2011045136A (ja) | 2011-03-03 |
JP5587144B2 true JP5587144B2 (ja) | 2014-09-10 |
Family
ID=26904271
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2002502605A Withdrawn JP2003536300A (ja) | 2000-06-06 | 2001-06-06 | スイッチマトリクスモジュールを備えたクロスポイントスイッチ |
JP2010255280A Expired - Fee Related JP5587144B2 (ja) | 2000-06-06 | 2010-11-15 | スイッチマトリクスモジュールを備えたクロスポイントスイッチ |
Family Applications Before (1)
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JP2002502605A Withdrawn JP2003536300A (ja) | 2000-06-06 | 2001-06-06 | スイッチマトリクスモジュールを備えたクロスポイントスイッチ |
Country Status (4)
Country | Link |
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US (2) | US6946948B2 (ja) |
EP (1) | EP1307820B1 (ja) |
JP (2) | JP2003536300A (ja) |
WO (1) | WO2001095120A1 (ja) |
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-
2001
- 2001-06-06 US US09/878,054 patent/US6946948B2/en not_active Expired - Lifetime
- 2001-06-06 WO PCT/US2001/040891 patent/WO2001095120A1/en active Application Filing
- 2001-06-06 JP JP2002502605A patent/JP2003536300A/ja not_active Withdrawn
- 2001-06-06 EP EP01942239.3A patent/EP1307820B1/en not_active Expired - Lifetime
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2005
- 2005-09-20 US US11/231,320 patent/US7236084B2/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
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US20060097841A1 (en) | 2006-05-11 |
US6946948B2 (en) | 2005-09-20 |
EP1307820B1 (en) | 2014-07-23 |
EP1307820A4 (en) | 2007-05-02 |
JP2003536300A (ja) | 2003-12-02 |
US7236084B2 (en) | 2007-06-26 |
US20020020905A1 (en) | 2002-02-21 |
JP2011045136A (ja) | 2011-03-03 |
EP1307820A1 (en) | 2003-05-07 |
WO2001095120A1 (en) | 2001-12-13 |
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