JP5571679B2 - 半導体材料を含む構造の品質を改善する方法 - Google Patents
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Description
Claims (15)
- 減少された数の表面転位を有する半導体構造を製作する方法であって、
半導体表面に現われる複数の発現表面転位の周りの表面乱れの範囲を拡大するステップと、
複数の発現表面転位の周りの表面の少なくとも乱れた部分を不連続なやり方で覆うように誘電体マスキング材料の層を堆積させるステップであって、前記表面の一部分はマスキング材料で覆われるが、前記表面の他の部分はそのように覆われない、ステップと、
実質的に連続した横方向範囲と減少された数の表面転位を有する次の半導体層を形成するステップと、
を含み、前記拡大するステップは、前記表面転位に関連した成長ピットの開きを助長するように選ばれた第1のエピタキシャル成長条件の下で中間半導体層を形成するステップをさらに含み、
前記半導体層を形成するステップは、前記成長ピットおよび前記成長ピットの凝集のいくらかまたは全てを密閉するための層を横方向成長させるステップをさらに含み、
前記横方向成長は、前記次の半導体層が実質的に連続した横方向範囲を有するまで少なくとも続き、
前記横方向成長は、前記マスキング材料の不連続層で覆われない成長ピットおよび成長ピットの凝集の一部分から核を成すことを特徴とする方法。 - 前記拡大するステップは、前記中間半導体層を形成するステップより前に、前記表面転位に関連したエッチングを助長するように選ばれた第1のエッチング条件の下で前記半導体表面をエッチングするステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記中間半導体層を形成するステップは、前記表面転位に関連した複数の成長ピットが交差して成長ピットの凝集になるのを助長するように選ばれた第2のエピタキシャル成長条件の下での成長をさらに含むことを特徴とする請求項1に記載の方法。
- 前記拡大するステップは、空洞の横方向範囲の増加および空洞の形成を助長するように選ばれた第1のエッチング条件の下で前記半導体表面をエッチングするステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記次の半導体層は、複数の発現表面転位の周りの前記表面乱れを密閉するのを助長するように選ばれた第3のエピタキシャル成長条件の下で形成されることを特徴とする請求項1に記載の方法。
- 前記拡大するステップ、前記堆積させるステップ、および前記形成するステップを1回または複数回繰り返すステップをさらに含むことを特徴とする請求項1に記載の方法。
- 前記誘電体マスキング材料の前記不連続層は、20オングストローム未満の厚さを有することを特徴とする請求項1に記載の方法。
- 前記拡大するステップ、前記堆積させるステップ、および前記形成するステップは、エクスサイチュ処理なしに単一反応炉チャンバ内で行われることを特徴とする請求項1に記載の方法。
- III−窒化物半導体構造を形成する方法であって、前記半導体構造が、複数の発現転位を有する最初のIII−窒化物表面を備え、前記方法が、
前記最初の表面上に成長する中間III−窒化物層中の、前記最初のIII−窒化物表面の表面転位に関連した成長ピットの開きを助長し、
前記成長する中間層中に開いた複数の前記成長ピットが交差して成長ピットの凝集になるのを助長し、さらに、
前記成長ピットおよび前記成長ピットの凝集のいくらかまたは全てを密閉するための次のIII−窒化物層の横方向成長を助長する
ように選ばれた一連のエピタキシャル成長条件に、前記最初の表面をさらすステップを含み、
前記横方向成長は、次の層が実質的に連続した横方向範囲を有するまで少なくとも続き、前記次の層は、前記最初の表面の転位密度よりも少ない転位密度で形成され、さらに、前記横方向成長は、誘電体マスキング材料の不連続層で覆われない成長ピットおよび成長ピットの凝集の一部分から核を成すことを特徴とする方法。 - 前記成長ピットの開きを助長する前記成長条件は、前記成長ピットの交差を助長する前記成長条件と実質的に似ていることを特徴とする請求項9に記載の方法。
- 前記成長ピットの開きおよび交差を助長する前記成長条件は、950℃未満の温度、100ミリバールを超える圧力、またはその両方を含むことを特徴とする請求項10に記載の方法。
- 前記一連の成長条件は、成長ピットの開きおよび交差を助長する条件より順序が後であるが横方向成長を助長する条件より順序が前である、前記誘電体マスク材料の成長を助長する条件をさらに含むことを特徴とする請求項9に記載の方法。
- 形成された前記III−窒化物層を前記成長チャンバから取り出すことなく、前記一連の成長条件を繰り返すステップをさらに含むことを特徴とする請求項9に記載の方法。
- 前記成長ピットの開きおよび交差は、複数の個々の成長ピットが5μm未満の横方向範囲を有する限り続くことを特徴とする請求項9に記載の方法。
- 前記誘電体マスキング材料の前記不連続層は、前記成長ピットおよび前記成長ピットの凝集の表面全体にわたって無秩序に分布されたシリコン窒化物を含むことを特徴とする請求項9に記載の方法。
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US11485508P | 2008-11-14 | 2008-11-14 | |
US61/114,855 | 2008-11-14 | ||
PCT/US2009/064330 WO2010056952A1 (en) | 2008-11-14 | 2009-11-13 | Methods for improving the quality of structures comprising semiconductor materials |
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US (1) | US8247314B2 (ja) |
EP (1) | EP2364504B1 (ja) |
JP (1) | JP5571679B2 (ja) |
KR (1) | KR101629733B1 (ja) |
CN (1) | CN102301447B (ja) |
WO (1) | WO2010056952A1 (ja) |
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US8329565B2 (en) * | 2008-11-14 | 2012-12-11 | Soitec | Methods for improving the quality of structures comprising semiconductor materials |
WO2011096684A2 (en) | 2010-02-04 | 2011-08-11 | Lg Siltron Inc. | Method for manufacturing galium naitride wafer |
FR2968678B1 (fr) | 2010-12-08 | 2015-11-20 | Soitec Silicon On Insulator | Procédés pour former des matériaux a base de nitrure du groupe iii et structures formées par ces procédés |
US9023721B2 (en) | 2010-11-23 | 2015-05-05 | Soitec | Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods |
FR2968830B1 (fr) | 2010-12-08 | 2014-03-21 | Soitec Silicon On Insulator | Couches matricielles ameliorees pour le depot heteroepitaxial de materiaux semiconducteurs de nitrure iii en utilisant des procedes hvpe |
FR2969815B1 (fr) * | 2010-12-27 | 2013-11-22 | Soitec Silicon On Insulator Tech | Procédé de fabrication d'un dispositif semi-conducteur |
KR20120079393A (ko) * | 2011-01-04 | 2012-07-12 | (주)세미머티리얼즈 | 반도체 발광소자의 제조방법 |
US8148252B1 (en) | 2011-03-02 | 2012-04-03 | S.O.I. Tec Silicon On Insulator Technologies | Methods of forming III/V semiconductor materials, and semiconductor structures formed using such methods |
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JP6301259B2 (ja) * | 2011-11-21 | 2018-03-28 | サン‐ゴバン、クリストー、エ、デテクトゥールSaint−Gobain Cristaux & Detecteurs | 半導体基板および形成方法 |
JP5881393B2 (ja) * | 2011-12-06 | 2016-03-09 | 国立大学法人山口大学 | 窒化物半導体発光素子およびその製造方法 |
CN102427102A (zh) * | 2011-12-06 | 2012-04-25 | 西安中为光电科技有限公司 | 一种防止外延层生长二次位错的方法 |
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US6534332B2 (en) | 2000-04-21 | 2003-03-18 | The Regents Of The University Of California | Method of growing GaN films with a low density of structural defects using an interlayer |
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