JP5558006B2 - 基板に形成された熱処理構造用の方法および装置 - Google Patents

基板に形成された熱処理構造用の方法および装置 Download PDF

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Publication number
JP5558006B2
JP5558006B2 JP2008558449A JP2008558449A JP5558006B2 JP 5558006 B2 JP5558006 B2 JP 5558006B2 JP 2008558449 A JP2008558449 A JP 2008558449A JP 2008558449 A JP2008558449 A JP 2008558449A JP 5558006 B2 JP5558006 B2 JP 5558006B2
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Prior art keywords
substrate
region
energy
regions
annealing
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JP2008558449A
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Japanese (ja)
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JP2009529245A5 (enExample
JP2009529245A (ja
Inventor
アブヒラッシュ マユール,
マーク ヤム,
アジット バラックリシュナ,
ポール キャリー,
ディーン ジェニングス,
スティーブン モファット,
ウィリアム シャファー,
アレキサンダー, エヌ. ラーナー,
ティモシー, エヌ. トーマス,
アーロン, ミュアー ハンター,
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Applied Materials Inc
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Applied Materials Inc
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Priority claimed from US11/459,852 external-priority patent/US20070221640A1/en
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Publication of JP2009529245A5 publication Critical patent/JP2009529245A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133Manufacturing common source or drain regions between multiple IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2008558449A 2006-03-08 2007-02-23 基板に形成された熱処理構造用の方法および装置 Expired - Fee Related JP5558006B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US78074506P 2006-03-08 2006-03-08
US60/780,745 2006-03-08
US11/459,856 2006-07-25
US11/459,847 2006-07-25
US11/459,852 2006-07-25
US11/459,852 US20070221640A1 (en) 2006-03-08 2006-07-25 Apparatus for thermal processing structures formed on a substrate
US11/459,847 US7569463B2 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
US11/459,856 US20070212859A1 (en) 2006-03-08 2006-07-25 Method of thermal processing structures formed on a substrate
PCT/US2007/062672 WO2007103643A2 (en) 2006-03-08 2007-02-23 Method and apparatus for thermal processing structures formed on a substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013231220A Division JP5931039B2 (ja) 2006-03-08 2013-11-07 基板に形成された熱処理構造用の方法および装置

Publications (3)

Publication Number Publication Date
JP2009529245A JP2009529245A (ja) 2009-08-13
JP2009529245A5 JP2009529245A5 (enExample) 2013-01-24
JP5558006B2 true JP5558006B2 (ja) 2014-07-23

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JP2008558449A Expired - Fee Related JP5558006B2 (ja) 2006-03-08 2007-02-23 基板に形成された熱処理構造用の方法および装置

Country Status (4)

Country Link
EP (1) EP1992013A2 (enExample)
JP (1) JP5558006B2 (enExample)
KR (2) KR101113533B1 (enExample)
WO (1) WO2007103643A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090120924A1 (en) * 2007-11-08 2009-05-14 Stephen Moffatt Pulse train annealing method and apparatus
US9498845B2 (en) 2007-11-08 2016-11-22 Applied Materials, Inc. Pulse train annealing method and apparatus
US9012315B2 (en) * 2013-08-09 2015-04-21 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
KR102216675B1 (ko) * 2014-06-12 2021-02-18 삼성디스플레이 주식회사 디스플레이 패널의 리페어 장치 및 디스플레이 패널의 리페어 방법
EP3611757A1 (en) * 2018-08-16 2020-02-19 Laser Systems & Solutions of Europe Method for forming a doped region on a semiconductor material

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696835A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Manufacture of semiconductor device
JPS5727035A (en) * 1980-07-25 1982-02-13 Hitachi Ltd Manufacture of semiconductor device
GB8515814D0 (en) * 1985-06-21 1985-07-24 British Telecomm Fabrication of optical waveguides
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
US5182170A (en) * 1989-09-05 1993-01-26 Board Of Regents, The University Of Texas System Method of producing parts by selective beam interaction of powder with gas phase reactant
JP3326654B2 (ja) * 1994-05-02 2002-09-24 ソニー株式会社 表示用半導体チップの製造方法
US5956603A (en) * 1998-08-27 1999-09-21 Ultratech Stepper, Inc. Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
US6525356B1 (en) * 1998-12-15 2003-02-25 Nec Corporation Solid imaging device
KR100338768B1 (ko) 1999-10-25 2002-05-30 윤종용 산화막 제거방법 및 산화막 제거를 위한 반도체 제조 장치
CN1194380C (zh) * 2000-04-24 2005-03-23 北京师范大学 绝缘体上单晶硅(soi)材料的制造方法
US6486066B2 (en) * 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
US6902966B2 (en) * 2001-10-25 2005-06-07 Advanced Micro Devices, Inc. Low-temperature post-dopant activation process
WO2003046967A2 (en) * 2001-11-30 2003-06-05 Koninklijke Philips Electronics N.V. Method of forming a doped region in a semiconductor body comprising a step of amorphization by irradiation
JP2003229568A (ja) * 2002-02-04 2003-08-15 Hitachi Ltd 半導体装置の製造方法および半導体装置
US7154066B2 (en) 2002-11-06 2006-12-26 Ultratech, Inc. Laser scanning apparatus and methods for thermal processing
JP2004363355A (ja) * 2003-06-05 2004-12-24 Hitachi Ltd 半導体装置及びその製造方法
US7098155B2 (en) 2003-09-29 2006-08-29 Ultratech, Inc. Laser thermal annealing of lightly doped silicon substrates
EP1524684B1 (en) * 2003-10-17 2010-01-13 Imec Method for providing a semiconductor substrate with a layer structure of activated dopants
JP4700324B2 (ja) * 2003-12-25 2011-06-15 シルトロニック・ジャパン株式会社 半導体基板の製造方法
EP1743390B1 (en) * 2004-04-27 2011-07-27 Creator Technology B.V. Method of forming an organic semiconducting device by a melt technique

Also Published As

Publication number Publication date
EP1992013A2 (en) 2008-11-19
KR101323222B1 (ko) 2013-10-30
WO2007103643B1 (en) 2008-06-26
WO2007103643A3 (en) 2008-05-08
JP2009529245A (ja) 2009-08-13
KR20100133454A (ko) 2010-12-21
WO2007103643A2 (en) 2007-09-13
KR20080104183A (ko) 2008-12-01
KR101113533B1 (ko) 2012-02-29

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