JPS5696835A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5696835A
JPS5696835A JP17118379A JP17118379A JPS5696835A JP S5696835 A JPS5696835 A JP S5696835A JP 17118379 A JP17118379 A JP 17118379A JP 17118379 A JP17118379 A JP 17118379A JP S5696835 A JPS5696835 A JP S5696835A
Authority
JP
Japan
Prior art keywords
mask
laser beam
chips
semiconductor device
annealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17118379A
Other languages
Japanese (ja)
Other versions
JPS6234131B2 (en
Inventor
Haruhisa Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17118379A priority Critical patent/JPS5696835A/en
Publication of JPS5696835A publication Critical patent/JPS5696835A/en
Publication of JPS6234131B2 publication Critical patent/JPS6234131B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To avoid the deterioration in the electric properties of the semiconductor device by selecting a beam region having energy density and uniformity adapted for an annealing when an ion implantation layer formed on a semiconductor wafer is annealed with a laser beam and treating chips one by one through a mask. CONSTITUTION:The laser beam 16 from a laser beam generator 11 is irradiated through a lens 12, a mirror 13 and the mask 14 on the semiconductor wafer 15 formed with a number of chips 151-155, and the layer in the chip is thus annealed. In this configuration the mask 14 is formed of two sheets of L-shaped members 141, 142, either of which is moved, thereby varying the size of an opening 14A formed. The size of the opening 14A is so formed that the beam 16 may not be irradiated to the adjacent chips to expose the periphery within the scribing line of each chip, and the beam 16 is selected from the beams for the region adapted for the annealing.
JP17118379A 1979-12-29 1979-12-29 Manufacture of semiconductor device Granted JPS5696835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17118379A JPS5696835A (en) 1979-12-29 1979-12-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17118379A JPS5696835A (en) 1979-12-29 1979-12-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5696835A true JPS5696835A (en) 1981-08-05
JPS6234131B2 JPS6234131B2 (en) 1987-07-24

Family

ID=15918535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17118379A Granted JPS5696835A (en) 1979-12-29 1979-12-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5696835A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009529245A (en) * 2006-03-08 2009-08-13 アプライド マテリアルズ インコーポレイテッド Method and apparatus for heat treatment structure formed on a substrate
JP2009200480A (en) * 2008-01-24 2009-09-03 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor substrate
US7772090B2 (en) * 2003-09-30 2010-08-10 Intel Corporation Methods for laser scribing wafers
JP2010245316A (en) * 2009-04-07 2010-10-28 Sumco Corp Method for manufacturing epitaxial wafer
JP2013232639A (en) * 2012-04-27 2013-11-14 Ultratech Inc Laser annealing scanning methods with reduced annealing non-uniformity
JP2014060423A (en) * 2006-03-08 2014-04-03 Applied Materials Inc Method and device for heat treated structure formed on substrate
CN106098599A (en) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 A kind of laser anneal device and control method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010033389A1 (en) * 2008-09-17 2010-03-25 Applied Materials, Inc. Managing thermal budget in annealing of substrates

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7772090B2 (en) * 2003-09-30 2010-08-10 Intel Corporation Methods for laser scribing wafers
US8364304B2 (en) 2003-09-30 2013-01-29 Intel Corporation Methods and apparatus for laser scribing wafers
JP2009529245A (en) * 2006-03-08 2009-08-13 アプライド マテリアルズ インコーポレイテッド Method and apparatus for heat treatment structure formed on a substrate
JP2014060423A (en) * 2006-03-08 2014-04-03 Applied Materials Inc Method and device for heat treated structure formed on substrate
US10141191B2 (en) 2006-03-08 2018-11-27 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
US10840100B2 (en) 2006-03-08 2020-11-17 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
JP2009200480A (en) * 2008-01-24 2009-09-03 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor substrate
JP2010245316A (en) * 2009-04-07 2010-10-28 Sumco Corp Method for manufacturing epitaxial wafer
JP2013232639A (en) * 2012-04-27 2013-11-14 Ultratech Inc Laser annealing scanning methods with reduced annealing non-uniformity
CN106098599A (en) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 A kind of laser anneal device and control method thereof

Also Published As

Publication number Publication date
JPS6234131B2 (en) 1987-07-24

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