JP5528667B2 - 半導体装置および半導体装置の制御方法 - Google Patents

半導体装置および半導体装置の制御方法 Download PDF

Info

Publication number
JP5528667B2
JP5528667B2 JP2007307760A JP2007307760A JP5528667B2 JP 5528667 B2 JP5528667 B2 JP 5528667B2 JP 2007307760 A JP2007307760 A JP 2007307760A JP 2007307760 A JP2007307760 A JP 2007307760A JP 5528667 B2 JP5528667 B2 JP 5528667B2
Authority
JP
Japan
Prior art keywords
gate electrode
region
impurity region
impurity
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007307760A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009135140A (ja
JP2009135140A5 (enExample
Inventor
龍太 土屋
俊明 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007307760A priority Critical patent/JP5528667B2/ja
Priority to US12/277,833 priority patent/US9287292B2/en
Publication of JP2009135140A publication Critical patent/JP2009135140A/ja
Publication of JP2009135140A5 publication Critical patent/JP2009135140A5/ja
Application granted granted Critical
Publication of JP5528667B2 publication Critical patent/JP5528667B2/ja
Priority to US15/018,533 priority patent/US20160156350A1/en
Priority to US15/251,238 priority patent/US11211406B2/en
Priority to US17/528,585 priority patent/US11695014B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2007307760A 2007-11-28 2007-11-28 半導体装置および半導体装置の制御方法 Active JP5528667B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007307760A JP5528667B2 (ja) 2007-11-28 2007-11-28 半導体装置および半導体装置の制御方法
US12/277,833 US9287292B2 (en) 2007-11-28 2008-11-25 Semiconductor device and method for controlling semiconductor device
US15/018,533 US20160156350A1 (en) 2007-11-28 2016-02-08 Semiconductor device and method for controlling semiconductor device
US15/251,238 US11211406B2 (en) 2007-11-28 2016-08-30 Semiconductor device and method for controlling semiconductor device
US17/528,585 US11695014B2 (en) 2007-11-28 2021-11-17 Semiconductor device and method for controlling semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007307760A JP5528667B2 (ja) 2007-11-28 2007-11-28 半導体装置および半導体装置の制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013230125A Division JP5745006B2 (ja) 2013-11-06 2013-11-06 半導体装置および半導体装置の制御方法

Publications (3)

Publication Number Publication Date
JP2009135140A JP2009135140A (ja) 2009-06-18
JP2009135140A5 JP2009135140A5 (enExample) 2010-10-14
JP5528667B2 true JP5528667B2 (ja) 2014-06-25

Family

ID=40668964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007307760A Active JP5528667B2 (ja) 2007-11-28 2007-11-28 半導体装置および半導体装置の制御方法

Country Status (2)

Country Link
US (4) US9287292B2 (enExample)
JP (1) JP5528667B2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014060420A (ja) * 2013-11-06 2014-04-03 Renesas Electronics Corp 半導体装置および半導体装置の制御方法
US9287292B2 (en) 2007-11-28 2016-03-15 Renesas Electronics Corporation Semiconductor device and method for controlling semiconductor device

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100062213A (ko) * 2008-12-01 2010-06-10 삼성전자주식회사 반도체 장치와 반도체 장치 제조 방법
JP2011040458A (ja) * 2009-08-07 2011-02-24 Renesas Electronics Corp 半導体装置およびその製造方法
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
EP2489075A4 (en) 2009-10-16 2014-06-11 Semiconductor Energy Lab LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE
WO2011062788A1 (en) * 2009-11-17 2011-05-26 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
WO2011068025A1 (en) * 2009-12-04 2011-06-09 Semiconductor Energy Laboratory Co., Ltd. Dc converter circuit and power supply circuit
JP5561823B2 (ja) * 2010-02-05 2014-07-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8299546B2 (en) * 2010-03-25 2012-10-30 International Business Machines Corporation Semiconductor devices with vertical extensions for lateral scaling
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8455875B2 (en) 2010-05-10 2013-06-04 International Business Machines Corporation Embedded DRAM for extremely thin semiconductor-on-insulator
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
JP2012129291A (ja) * 2010-12-14 2012-07-05 Renesas Electronics Corp 半導体集積回路装置
JP5661445B2 (ja) 2010-12-14 2015-01-28 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびその製造方法
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
EP2498280B1 (en) * 2011-03-11 2020-04-29 Soitec DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
WO2012132219A1 (ja) * 2011-03-29 2012-10-04 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8658506B1 (en) 2011-04-06 2014-02-25 Qualcomm Incorporated Method and apparatus for selectively improving integrated device performance
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
KR101909696B1 (ko) 2011-05-16 2018-12-19 마벨 월드 트레이드 리미티드 고전압 스타트업 회로
US20120313692A1 (en) * 2011-06-08 2012-12-13 Sehat Sutardja Super-high-voltage resistor on silicon
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
JP5690683B2 (ja) 2011-07-22 2015-03-25 ルネサスエレクトロニクス株式会社 半導体装置
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US9054221B2 (en) * 2011-08-31 2015-06-09 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with a common back gate isolation region and method for manufacturing the same
CN102956703B (zh) * 2011-08-31 2016-03-30 中国科学院微电子研究所 半导体器件及其制造方法
FR2980035B1 (fr) * 2011-09-08 2013-10-04 Commissariat Energie Atomique Circuit integre realise en soi comprenant des cellules adjacentes de differents types
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
JP5847549B2 (ja) 2011-11-16 2016-01-27 ルネサスエレクトロニクス株式会社 半導体装置
FR2983345A1 (fr) * 2011-11-30 2013-05-31 Soitec Silicon On Insulator Grille arriere unifiee
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8987073B2 (en) 2012-07-11 2015-03-24 International Business Machines Corporation Self-protected metal-oxide-semiconductor field-effect transistor
FR2993403B1 (fr) * 2012-07-13 2014-08-22 Commissariat Energie Atomique Circuit integre sur soi comprenant un triac de protection contre des decharges electrostatiques
FR2993405B1 (fr) 2012-07-13 2014-08-22 Commissariat Energie Atomique Circuit integre sur soi comprenant un transistor de protection sous-jacent
JP6003363B2 (ja) * 2012-08-03 2016-10-05 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
JP6100535B2 (ja) * 2013-01-18 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9219078B2 (en) 2013-04-18 2015-12-22 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
JP2014232810A (ja) * 2013-05-29 2014-12-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
JP6076224B2 (ja) 2013-09-05 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20150129967A1 (en) * 2013-11-12 2015-05-14 Stmicroelectronics International N.V. Dual gate fd-soi transistor
CN104810396B (zh) * 2014-01-23 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US9800204B2 (en) 2014-03-19 2017-10-24 Stmicroelectronics International N.V. Integrated circuit capacitor including dual gate silicon-on-insulator transistor
JP2015222607A (ja) 2014-05-22 2015-12-10 ルネサスエレクトロニクス株式会社 半導体装置
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
KR102277398B1 (ko) * 2014-09-17 2021-07-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP6316725B2 (ja) * 2014-10-03 2018-04-25 ルネサスエレクトロニクス株式会社 半導体装置
JP6340310B2 (ja) 2014-12-17 2018-06-06 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびウェラブル装置
US9972395B2 (en) * 2015-10-05 2018-05-15 Silicon Storage Technology, Inc. Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems
JP6501695B2 (ja) 2015-11-13 2019-04-17 ルネサスエレクトロニクス株式会社 半導体装置
US10096602B1 (en) * 2017-03-15 2018-10-09 Globalfoundries Singapore Pte. Ltd. MTP memory for SOI process
JP2019029558A (ja) 2017-08-01 2019-02-21 ソニーセミコンダクタソリューションズ株式会社 トランジスタ及び電子機器
US10535775B2 (en) * 2018-05-30 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon on insulator semiconductor device with mixed doped regions
FR3098986B1 (fr) * 2019-07-15 2023-01-27 St Microelectronics Sa Protection d’un circuit intégré contre un percement d’un contact source et/ou drain
US12453182B2 (en) 2019-11-15 2025-10-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
FR3106019B1 (fr) * 2020-01-07 2021-12-10 Soitec Silicon On Insulator Procede de fabrication d’une structure de type semi-conducteur sur isolant pour applications radiofréquences
US11600628B2 (en) * 2020-01-15 2023-03-07 Globalfoundries U.S. Inc. Floating gate memory cell and memory array structure
US12040399B2 (en) 2022-03-17 2024-07-16 Renesas Electronics Corporation Semiconductor device

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04352467A (ja) * 1991-05-30 1992-12-07 Toshiba Corp Ｍｏｓ型半導体集積回路装置
US5359219A (en) * 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
JPH07106579A (ja) 1993-10-08 1995-04-21 Hitachi Ltd 半導体装置とその製造方法
JP3376204B2 (ja) 1996-02-15 2003-02-10 株式会社東芝 半導体装置
JPH10242460A (ja) * 1997-02-25 1998-09-11 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH1145995A (ja) * 1997-07-25 1999-02-16 Nec Kyushu Ltd 半導体装置およびその製造方法
JP2001015696A (ja) * 1999-06-29 2001-01-19 Nec Corp 水素バリヤ層及び半導体装置
JP3437132B2 (ja) 1999-09-14 2003-08-18 シャープ株式会社 半導体装置
KR100350575B1 (ko) * 1999-11-05 2002-08-28 주식회사 하이닉스반도체 소오스-바디-기판이 접촉된 이중막 실리콘 소자 및 제조방법
JP3547361B2 (ja) 2000-03-31 2004-07-28 株式会社東芝 半導体装置
US6503783B1 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. SOI CMOS device with reduced DIBL
US6596570B2 (en) * 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
JP2004172541A (ja) * 2002-11-22 2004-06-17 Renesas Technology Corp 半導体装置の製造方法
JP4850387B2 (ja) 2002-12-09 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
JP4446690B2 (ja) 2003-06-27 2010-04-07 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP4282388B2 (ja) 2003-06-30 2009-06-17 株式会社東芝 半導体記憶装置
JP2005051140A (ja) 2003-07-31 2005-02-24 Toshiba Corp 半導体装置およびその製造方法
JP2005251776A (ja) 2004-03-01 2005-09-15 Renesas Technology Corp 半導体装置とその製造方法
US6872640B1 (en) * 2004-03-16 2005-03-29 Micron Technology, Inc. SOI CMOS device with reduced DIBL
US7382023B2 (en) * 2004-04-28 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fully depleted SOI multiple threshold voltage application
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US7091079B2 (en) * 2004-11-11 2006-08-15 United Microelectronics Corp. Method of forming devices having three different operation voltages
JP2006245417A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 半導体装置およびその製造方法
WO2007004535A1 (ja) 2005-07-05 2007-01-11 Renesas Technology Corp. 半導体装置およびその製造方法
US7314794B2 (en) 2005-08-08 2008-01-01 International Business Machines Corporation Low-cost high-performance planar back-gate CMOS
US7504289B2 (en) * 2005-10-26 2009-03-17 Freescale Semiconductor, Inc. Process for forming an electronic device including transistor structures with sidewall spacers
JP5105462B2 (ja) * 2005-12-27 2012-12-26 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2007180402A (ja) 2005-12-28 2007-07-12 Toshiba Corp 半導体装置及びその製造方法
JP2007242950A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体記憶装置
JP2008047706A (ja) * 2006-08-16 2008-02-28 Nec Lcd Technologies Ltd 半導体回路及びそれを用いた半導体装置
KR100766500B1 (ko) * 2006-10-20 2007-10-15 삼성전자주식회사 반도체 소자 및 그 형성 방법
JP5528667B2 (ja) 2007-11-28 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の制御方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9287292B2 (en) 2007-11-28 2016-03-15 Renesas Electronics Corporation Semiconductor device and method for controlling semiconductor device
US11211406B2 (en) 2007-11-28 2021-12-28 Renesas Electronics Corporation Semiconductor device and method for controlling semiconductor device
US11695014B2 (en) 2007-11-28 2023-07-04 Renesas Electronics Corporation Semiconductor device and method for controlling semiconductor device
JP2014060420A (ja) * 2013-11-06 2014-04-03 Renesas Electronics Corp 半導体装置および半導体装置の制御方法

Also Published As

Publication number Publication date
US20220077191A1 (en) 2022-03-10
US20160156350A1 (en) 2016-06-02
US9287292B2 (en) 2016-03-15
US20160372486A1 (en) 2016-12-22
US11211406B2 (en) 2021-12-28
JP2009135140A (ja) 2009-06-18
US11695014B2 (en) 2023-07-04
US20090134468A1 (en) 2009-05-28

Similar Documents

Publication Publication Date Title
JP5528667B2 (ja) 半導体装置および半導体装置の制御方法
US7880231B2 (en) Integration of a floating body memory on SOI with logic transistors on bulk substrate
CN101160667B (zh) 改进单元稳定性和性能的混合块soi 6t-sram单元
JP2012169640A (ja) 半導体装置
SG183451A1 (en) Thyristor-based memory cells, devices and systems including the same and methods for forming the same
TW200843111A (en) Floating body memory cell having gates favoring different conductivity type regions
JP5364108B2 (ja) 半導体装置の製造方法
JP2009212413A (ja) 半導体装置及び半導体装置の製造方法
JP2023073971A (ja) 半導体構造、方法（代替用埋め込みパワーレール）
JP6467472B2 (ja) 半導体装置
JP5081394B2 (ja) 半導体装置の製造方法
JP5745006B2 (ja) 半導体装置および半導体装置の制御方法
JP6174370B2 (ja) 半導体装置
US20090189198A1 (en) Structures of sram bit cells
JP6203915B2 (ja) 半導体装置
JP2015164214A (ja) 半導体装置および半導体装置の制御方法
JP4093072B2 (ja) 半導体装置およびその製造方法
JP3487220B2 (ja) 電界効果型トランジスタ及び半導体装置
JP2001036037A (ja) 半導体装置及び半導体装置の製造方法
JP2014096442A (ja) 半導体装置
JP2002057336A (ja) 半導体装置及びその製造方法
JP2009170718A (ja) 半導体装置
JP2009004595A (ja) 半導体装置及び当該半導体装置を具備する電子機器

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100524

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100830

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100830

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120817

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120828

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121029

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121113

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131106

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20131113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140128

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140326

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140415

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140416

R150 Certificate of patent or registration of utility model

Ref document number: 5528667

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350