JP5522551B2 - Circuit member manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a circuit member used in the resin sealed semiconductor device mounting a semiconductor device (plastic package), in particular, it corresponds to the package size, is possible to improve the mountability The present invention relates to a method for manufacturing a circuit member used in a semiconductor device.

In recent years, semiconductor devices are becoming increasingly integrated and highly integrated, as represented by LSI ASICs, due to the trend of high integration and miniaturization technology and the trend of high performance and light and thin electronic devices (current). It is becoming functional.
As a result, even in a sealed semiconductor device using a lead frame, the development trend has progressed through surface-mounted packages such as SOJ (Small Outline J-Leaded Package) and QFP (Quad Flat Package). , TSOP (Thin Small Outline Package) development to reduce the size of the package with the main axis being thin, and further to the LOC (Lead On Chip) structure for the purpose of improving chip storage efficiency by making the inside of the package three-dimensional Has progressed.
However, resin-encapsulated semiconductor devices are required to have higher integration, higher functionality, and even higher pin counts, thickness reductions, and downsizing. Due to the routing, the limit to the miniaturization of the package has been seen.

            JP-A-11-251504

As described above, there is a demand for higher integration and higher functionality of resin-encapsulated semiconductor devices, and there is a need for further increase in the number of pins, thickness, and size of resin-encapsulated semiconductor devices. .
Under such circumstances, the present invention can increase the chip occupancy ratio in the package size of the semiconductor device, cope with the miniaturization of the semiconductor device, and reduce the mounting area on the circuit board. is intended to provide a manufacturing how a circuit member used in the resin-encapsulated semiconductor device capable of improving the mounting density.

The resin-encapsulated semiconductor device according to the present invention includes a resin-encapsulated semiconductor device that is resin-encapsulated by exposing at least a part of the external terminals, or an external terminal that is exposed to the outside of the resin-encapsulated semiconductor device. A resin-encapsulated semiconductor device in which external electrodes made of solder for mounting on a circuit board or the like are provided on the surface of the part, and an internal terminal part for electrically connecting with a terminal of a semiconductor element, and an external It has an external terminal part for connection to a circuit, and a lead part that integrally connects the internal terminal part and the external terminal part, and the internal terminal part and the external terminal part are provided separately on the front and back, The internal terminal portion and the lead portion are formed to be thin, and the external terminal portion is formed to be thick.A plurality of terminal members are independent from each other, and the terminal surface of the internal terminal portion of each terminal member is Equipped with a circuit unit arranged in one plane in the same direction The surface on the terminal portion side of the semiconductor element and the surface on the internal terminal portion side of the circuit portion face each other, and the semiconductor element is joined or brought into contact with the surface on the terminal surface side of the internal terminal of the circuit portion at the terminal portion. The terminal portion and the internal terminal portion of the circuit portion are electrically connected.
The resin-encapsulated semiconductor device is characterized in that the protruding electrode in the terminal portion of the semiconductor element is joined or in contact with the surface on the terminal surface side of the internal terminal of the circuit portion. It is.
Further, in any of the above resin-encapsulated semiconductor devices, the terminal portion of the semiconductor element and the internal terminal portion of the circuit portion are connected via a metal plating layer for connection provided on the terminal surface of the internal terminal portion. Thus, the terminal portion of the semiconductor element and the internal terminal portion of the circuit portion are joined and electrically connected.
In the above, at least one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, and a palladium plating layer is used for connecting the terminal portion of the semiconductor element and the internal terminal portion of the circuit member. The metal plating layer is characterized in that the metal plating layer is formed only on the terminal surface of the internal terminal portion of the circuit portion facing the semiconductor element.
Alternatively, in any of the above resin-encapsulated semiconductor devices, the terminal portion of the semiconductor element and the internal terminal portion of the circuit portion are connected via a paste layer for connection provided on the terminal surface of the internal terminal portion. The terminal portion of the semiconductor element and the internal terminal portion of the circuit portion are joined and electrically connected.

Circuit member according to the present onset Ming is entirely a circuit member for a substantially flat-shaped resin-sealed semiconductor device, the internal terminal portion for connecting the terminals and the electrically semiconductor element, connection to an external circuit An external terminal portion, and a lead portion that integrally connects the internal terminal portion and the external terminal portion, and the internal terminal portion and the external terminal portion are provided separately on the front and back, the internal terminal portion, A plurality of terminal members, each having a thin lead portion and a thick external terminal portion, are independent of each other, and the terminal surfaces of the internal terminal portions of each terminal member are aligned in the same direction. Further, the outer frame portion is provided so as to be arranged on a plane and to be integrally connected to an external terminal portion via a connection lead different from the lead portion on the outside thereof, and to hold the whole. Is.
And it is said circuit member, Comprising: A metal plate material is formed by the half etching processing method, It is characterized by the above-mentioned.
Further, any of the above circuit members, wherein a metal plating layer is formed on a terminal surface of the internal terminal portion for connection between the terminal portion of the semiconductor element and the internal terminal portion of the circuit member. For connecting at least one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, and a palladium plating layer between the terminal portion of the semiconductor element and the internal terminal portion of the circuit member. It is characterized by being a metal plating layer.
Alternatively, in any one of the circuit members described above, a paste layer is formed on the terminal surface of the internal terminal portion for connection between the terminal portion of the semiconductor element and the internal terminal portion of the circuit member. And the paste is a Pb-free paste.
In addition, the etching process method accompanied by a half etching process is called a half etching process method here.

In the method for manufacturing a circuit member of the present invention, a resin-encapsulated semiconductor device in which at least a part of an external terminal portion is exposed to the outside and resin-sealed, or an external terminal portion exposed to the outside of the resin-encapsulated semiconductor device is disclosed. This is a resin-encapsulated semiconductor device provided with an external electrode made of solder for mounting on a circuit board or the like on the surface, and a flip chip is connected to the internal terminal portion integrally connected to the external terminal at the terminal of the semiconductor element It is a CSP (Chip Size Package), which is a CSP (Chip Size Package) that has a structure to be connected and a resin-encapsulated region substantially matched to the size of the semiconductor element. An internal terminal portion for electrically connecting to a terminal of the semiconductor element; an external terminal portion for connection to an external circuit; and a lead portion for integrally connecting the internal terminal portion and the external terminal portion. And inside The terminal part and the external terminal part are provided separately on the front and back, the internal terminal part and the lead part are formed thin, and the external terminal part is formed thick. In addition, the terminal surfaces of the internal terminal portions of the respective terminal members are arranged in a single plane in the same direction, and are further integrally connected to the external terminal portions via connection leads different from the lead portions on the outside thereof. An outer frame portion that holds the whole, and the plurality of terminal members are connected to opposing sides of the outer frame portion, and the external terminal portions of the terminal members are connected to the outer frame portions. For each side facing each other, arrange in two rows in parallel along the side of the outer frame portion to be connected, and the external terminal portions of adjacent terminal members are in different rows from each other. is, the circuit member, a manufacturing method for manufacturing circuitry member, A metal plate is used as a raw material, and selective etching is performed from both sides of the raw material simultaneously. The outer terminal portion is made of a material plate thickness, the outer shape is processed, and a metal plating layer for flip connection with a semiconductor element is formed on the terminal surface of the inner terminal portion by plating. The metal plating layer for flip connection with the semiconductor element is formed by coating the whole with a photosensitive electrodeposition resist after the outer shape processing, making a predetermined opening corresponding to the plating region, and using this as a plating mask. In this case, the plating is performed only on the region exposed from the opening, and the partial plating method is used.

(Function)
The resin-encapsulated semiconductor device according to the present invention is configured as described above, so that the chip occupancy in the semiconductor device package size can be increased and the semiconductor device can be made smaller.
That is, the mounting area of the semiconductor device on the circuit board can be reduced, and the mounting density on the circuit board can be improved.
By forming the external electrode portion integrally connected to the external terminal portion with a solder ball, a BGA (Ball Grid Array) type may be used.
Specifically, an internal terminal portion for electrical connection with a terminal of a semiconductor element, an external terminal portion for connection to an external circuit, and the internal terminal portion and the external terminal portion are integrally coupled. A lead member, an internal terminal portion and an external terminal portion are provided separately on the front and back, the internal terminal portion, the lead portion is formed thin, and the external terminal portion is formed thick, a terminal member, A plurality of circuit parts are provided independently of each other and arranged so that the terminal surfaces of the internal terminal parts of the terminal members are aligned on the same plane in the same direction, the terminal part side surface of the semiconductor element and the circuit part The semiconductor element is bonded or contacted to the terminal surface side surface of the internal terminal of the circuit portion at the terminal portion, so that the terminal portion of the semiconductor element and the internal terminal portion of the circuit portion are connected to each other. This is achieved by being electrically connected.
That is, the terminal surface of the external terminal portion protrudes from the internal terminal portion and the lead portion on the side opposite to the semiconductor element of the circuit portion, and the external terminal portion is two-dimensionally along the surface direction along the terminal surface of the semiconductor element. The terminal surface can be formed at a practical level to increase the number of terminals of semiconductor devices and to reduce the pitch.
In other words, the resin-encapsulated semiconductor device can cope with an increase in the number of pins. In particular, by using a CSP (Chip Size Package) in which the resin sealing region is substantially matched to the outer dimensions of the semiconductor element, the semiconductor device can be reduced in size.
Further, by exposing not only the terminal surface of the external terminal but also a part including the side surface portion to the outside, the entire thickness can be reduced and heat dissipation can be improved.
Further, the terminals of the semiconductor element are arranged along the center line in the middle of the pair of sides of the terminal surface of the semiconductor element, and the internal terminal part of the circuit part is opposed to sandwich the center line, and the center line is opposed to the center line. By adopting a structure provided along each, the entire structure can be made simple and suitable for mass production.

This onset involving bright circuitry member, by the configuration as described above, but is used in the manufacture of a resin encapsulated semiconductor device of the present invention, cormorants併half etching typical etching process It can be manufactured through.

With such a configuration , the circuit member manufacturing method of the present invention exposes at least a part of the external terminal portion to the outside and is resin-sealed with a resin-sealed semiconductor device, or outside the resin-sealed semiconductor device. A resin-encapsulated semiconductor device in which an external electrode made of solder for mounting on a circuit board or the like is provided on the surface of an exposed external terminal portion, and an internal connection integrally with the external terminal at a terminal of a semiconductor element A flip-chip connection structure to the terminal portion, and a CSP (Chip Size Package) in which the resin sealing region is almost matched to the size of the semiconductor element. In this circuit member, an internal terminal portion for electrical connection with a terminal of a semiconductor element, an external terminal portion for connection to an external circuit, and the internal terminal portion and the external terminal portion are integrally coupled. The inner terminal portion and the outer terminal portion are provided separately on the front and back, the inner terminal portion and the lead portion are formed thin, and the outer terminal portion is formed thick. A plurality of terminal leads, which are independent from each other and arranged so that the terminal surfaces of the internal terminal portions of the respective terminal members are aligned in the same direction on a single plane, and on the outside thereof, connection leads different from the lead portions. It is possible to manufacture a circuit member having an outer frame portion that is integrally connected to an external terminal portion via a pin to hold the whole, and as a result, a resin-encapsulated semiconductor device according to the present invention can be manufactured. It is what.

As described above, the present invention increases the chip occupancy in the package size of the semiconductor device under the situation where further integration and higher functionality of the resin-encapsulated semiconductor device are required. Accordingly, it is possible to provide a method for manufacturing a circuit member used in a conductor device that can reduce the mounting area on a circuit board, that is, improve the mounting density on the circuit board.

FIG. 1A is a schematic cross-sectional view showing one cross-section of an example of an embodiment of a resin-encapsulated semiconductor device according to the present invention, and FIG. 1B is an external electrode side (FIG. 1A It is the figure seen from the A0 side). FIG. 2 is a perspective view showing an external electrode side and a side surface portion of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1. 4 (a) is a schematic plan view of an example of embodiment of the circuit member according to the present onset bright, in FIG. 4 (b) FIG. 4 (a), the enlarged perspective of B1 parts enclosed by the dotted line FIG. It is process sectional drawing of one example of embodiment of the manufacturing method of the circuit member of this invention. FIG. 2 is a process cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic cross-sectional view showing one cross-section of an example of an embodiment of a resin-encapsulated semiconductor device according to the present invention, and FIG. 1B is an external electrode side (FIG. 1A 2) is a perspective view showing the external electrode side and the side surface portion of the semiconductor device shown in FIG. 1 in an easy-to-understand manner. FIGS. 3 (a) and 3 (b) are respectively 4 is a cross-sectional view of a modification of the semiconductor device shown in FIG. 1, FIG. 4 (a) is a schematic plan view of one example of an embodiment of a circuit member according to the present invention , and FIG. 4 (b) is FIG. 5 is an enlarged perspective view of a portion B1 surrounded by a dotted line, FIG. 5 is a process sectional view of an example of an embodiment of a method for manufacturing a circuit member of the present invention, and FIG. 6 is a diagram of the semiconductor device shown in FIG. It is process sectional drawing which showed the manufacturing process.
1A is a cross-sectional view taken along line A1-A2 of FIG.
1 to 6, reference numerals 100, 101, and 102 denote resin-encapsulated semiconductor devices, 110 denotes a semiconductor element, 110S denotes a terminal surface, 115 denotes a terminal (pad), 130 denotes a circuit member, 130A denotes a terminal member, and 130B denotes a circuit. Part, 130S is a material surface, 130a is a circuit member, 131 is an internal terminal part, 131S is a terminal surface (of the internal terminal part), 132 is an external terminal part, 132S is a terminal surface (of the external terminal part), 133 is a lead, 134 is a connection lead, 135 is a frame portion, 138 is a metal plating layer, 150 is a sealing resin, 170 is an external electrode made of solder, 510 is a metal plate, 520 is a resist layer, 521 and 522 are resist patterns, and 530 is It is a thin part.

First, an example of a resin-encapsulated semiconductor device according to the present invention will be described with reference to FIGS.
In the resin-encapsulated semiconductor device 100 of this example shown in FIG. 1, a part (terminal surface) of the external terminal 132 is exposed to the outside, the resin is sealed with a sealing resin 150, and the external terminal is exposed to the outside. 4 is a resin-encapsulated semiconductor device in which an external electrode 170 made of solder for mounting on a circuit board or the like is provided on the terminal surface 132S of the part 132, and only the area B2 within the dotted line of the circuit member 130 shown in FIG. Are sealed with resin, and parts other than the B2 region are cut and separated.
Then, the internal terminal 131 for electrically connecting to the terminal 115 of the semiconductor element 110, the external terminal 132 for connection to an external circuit, the internal terminal 131 and the external terminal 132 are integrally formed. The internal terminal portion 131 and the external terminal portion 132 are provided separately on the front and back, the internal terminal portion 131 and the lead portion 133 are formed thin, and the external terminal portion 132 is thick. A plurality of formed terminal members 130A are provided independently of each other, and provided with a circuit portion 130B in which the terminal surfaces 131S of the internal terminal portions 131 of the terminal members 130A are arranged in one plane in the same direction. The surface of the semiconductor element 110 on the side of the terminal portion 115 faces the surface of the circuit portion 130B on the side of the internal terminal portion 131, and the semiconductor element 110 has the terminal portion 115 of the circuit portion 130B. Bonded to the surface of the terminal surface 131S side parts terminal portion 131, the internal terminal portion 131 of the terminal portion 115 and the circuit portion 130B of the semiconductor element 110 are electrically connected.
As shown in FIG. 1A, the terminal surface 132S of the external terminal part 132 protrudes from the internal terminal part 131 and the lead part 133 on the side opposite to the semiconductor element 110 of the circuit part 130B. The terminal surface 132S of the external terminal portion 132 is formed two-dimensionally in the surface direction along the terminal surface 132.
Since the semiconductor device of this example uses the circuit member 130 shown in FIG. 4, the connection lead 134 is left inside.

The circuit portion 130B used here is inside the one-dot chain line region B2 of the circuit member 130 shown in FIG.
In the semiconductor device 100 of the present example, one surface side (first surface side) of the circuit unit 130B is formed as a material surface 130S on substantially the same plane (plane S1). The terminal surface 131S is also a material surface and is formed on the plane S1.

In this example, a connection metal plating layer 138 is provided on the terminal surface 131S of the internal terminal portion 131 of the circuit portion 130B, and the terminal portion 115 of the semiconductor element 110 and the internal terminal portion 131 of the circuit portion 130B are interposed therebetween. The terminal surface 131S is joined.
As the metal plating layer 138, at least one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, and a palladium plating layer is formed on the terminal surface of the internal terminal portion 131 of the circuit portion 130B. The terminal part 115 of the semiconductor element 110 and the terminal surface 131S of the internal terminal part 131 of the circuit part 130B are joined by solder reflow, metal eutectic, thermocompression bonding, or the like.

In the resin-encapsulated semiconductor device 100 shown in FIG. 1, the terminal portion 115 of the semiconductor element 110 is disposed along the center line between the pair of sides of the terminal surface of the semiconductor element 110, and the internal terminal portion 131. Are opposite each other so as to sandwich the center line, and are provided along the center line.
Further, in the resin-encapsulated semiconductor device 100 shown in FIG. 1, the resin-encapsulated region has a structure substantially matched to the size of the semiconductor element and is called a CSP (Chip Size Package).

As a modification of this example, a circuit member in which a paste layer for connection is formed on the terminal surface 131S of the internal terminal portion 131 of the circuit portion 130B is used, and the terminal portion 115 of the semiconductor element 110 and the circuit are interposed therebetween. The thing which joined the terminal surface 131S of the internal terminal part 131 of the part 130B is also mentioned.
In this case, the paste is preferably a Pb-free paste.

Incidentally, as an embodiment of the resin-sealed semiconductor device according to the present onset Ming, shown in Figure 1, it is not particularly limited to CSP type.
Further, as shown in FIG. 3A, the semiconductor device shown in FIG. 1 in which the external electrode made of solder is not provided is cited as a semiconductor device 101 of a modified example.
Further, as shown in FIG. 3B, the connection lead 134 may be made of a material thickness similar to the external terminal portion 132.
In this case, compared to the example shown in FIG. 1, but becomes excellent in terms of heat dissipation, cut and separated from the frame portion 135 of the circuit member 130 shown in FIG. 4 is somewhat difficult.

  As a material of the circuit unit 130B, a Ni-iron alloy (for example, Ni42% -Fe alloy), a copper alloy, or the like is used.

It will now be described with reference to one example of embodiment of the circuit member according to the present onset bright in FIG.
As previously described, the one-dot chain line region B2 in FIG. 4 is a region that is used by sealing with a resin when manufacturing a semiconductor device of a circuit member, and the region outside the one-dot chain line is finally Separated and removed.
The circuit member 130 of this example is a substantially flat circuit member used for manufacturing the semiconductor device shown in FIG. 1 and has no metal plating layer disposed on the terminal surface of the internal terminal portion. It is.
As shown in FIG. 4A, the circuit member 130 of the present example includes an internal terminal portion 131 for electrically connecting to a terminal of a semiconductor element, an external terminal portion 132 for connecting to an external circuit, The internal terminal portion 131 and the external terminal portion 132 are integrally connected to each other, and the internal terminal portion 131 and the external terminal portion 132 are separately provided on the front and back sides of the internal terminal portion 131 and the external terminal portion 132. The external terminal 132 is formed to be thick, and a plurality of terminal members are formed independently of each other, and the terminal surfaces 131S of the internal terminal portions 131 of the terminal members are oriented in the same direction. Further, an outer frame portion 135 is provided which is arranged so as to be aligned on a single plane and is integrally connected to the external terminal portion 132 via a connection lead 134 different from the lead portion 133 on the outside thereof, and holds the whole. .
As shown in FIG. 4B, the terminal surface 132S of the external terminal portion 132 protrudes from the internal terminal portion 131 and the lead portion 133 on the side opposite to the semiconductor element 110 of the circuit portion 130B. A terminal surface 132S of the external terminal portion 132 is formed two-dimensionally in the surface direction along the terminal surface 110S.
In the circuit member of this example, the surface on the terminal surface side of the circuit member 130 (the first surface in FIG. 1A) is the material surface 130S.
As a material of the circuit member 130, a Ni-iron alloy (for example, Ni42% -Fe alloy), a copper alloy, or the like is used, and the outer shape can be processed by etching as in a normal lead frame.

A metal plating layer formed on the terminal surface of the internal terminal of the circuit member 130 shown in FIG. 4 for connection between the terminal portion of the semiconductor element and the internal terminal portion of the circuit member is used for the semiconductor device shown in FIG. The circuit member used.
For connecting at least one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a silver-tin plating layer between a terminal portion of a semiconductor element and an internal terminal portion of a circuit member The metal plating layer.
Moreover, what formed the paste layer in the terminal surface of the internal terminal of the circuit member 130 shown in FIG. 4 for the connection of the terminal part of a semiconductor element and the internal terminal part of a circuit member is also mentioned as a circuit member.
A semiconductor device using the circuit member is the above-described modified semiconductor device.

Next, an example of a method for manufacturing the circuit member 130 shown in FIG. 4 will be described with reference to FIG.
Note that FIG. 5 shows only a cross section taken along one-dot chain line B3-B4 shown in FIG.
First, a metal plate 510 having a thickness of about 0.2 mm, which is a material of a circuit member, made of 42 alloy (Ni 42% Fe alloy), copper alloy, etc. is prepared (FIG. 5A), and both surfaces of the metal plate 510 are prepared. After degreasing and cleaning the substrate, a photosensitive resist is applied to both surfaces of the metal plate 510 and dried to form a resist layer 520. (Fig. 5 (b))
Next, after exposing only a predetermined portion of the resist layer 520 from both surfaces of the metal plate 510 using a predetermined pattern plate, development processing is performed to form resist patterns 521 and 522. (Fig. 5 (c))
In the formation region of the internal terminal portion, the lead portion, and the connection lead portion, the resist is not covered on one side of the plate material.
The resist is not particularly limited, but a casein resist using potassium dichromate as a photosensitizer, a negative liquid resist (PMER resist) manufactured by Tokyo Ohka Co., Ltd., or the like can be used.
Next, the resist pattern is used as an anticorrosion film, and etching is performed from both surfaces of the plate material 510 with an etching solution.
In the formation region of the internal terminal portion, the lead portion, and the connection lead portion, the etching proceeds only from one side because the resist on one side of the plate material is not covered. (This is called half-etching here.)
The thickness of the thin portion 530 can be adjusted by adjusting the etching amount of the front and back surfaces of the plate material 510.
Etching is usually performed by spray etching from both sides of the plate material using a ferric chloride aqueous solution as a corrosive solution.
In the middle of the etching, as shown in FIG. 5D, the etching progresses further and the internal terminal portions 131 are separated from each other, so that one surface is the material surface 510S of the plate material 510, and the internal terminal portions 131, leads The part 133 and the connection lead part 134 are formed thinner than the thickness of the material of the plate material 510, and the external terminal part 132 and the outer frame portion 134 are formed to the same thickness as the thickness of the material of the plate material 510. (Fig. 5 (e))
Next, the resist is peeled off (FIG. 5F), and the circuit member 130 shown in FIG. 4 is obtained.

Next, partial plating is performed on the terminal surface of the internal terminal portion of the circuit member 130, and the circuit member 130a provided with the metal plating layer 138 used in the semiconductor device shown in FIG. 1 is obtained. (Fig. 5 (g))
As the metal plating layer 138, at least one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, and a palladium plating layer is formed on the terminal surface of the internal terminal portion 131 of the circuit portion 130B.
This partial plating is performed only on the terminal surface of the internal terminal using a photosensitive electrodeposition resist.
Alternatively, a paste layer for connecting to the terminal of the semiconductor element is formed on the terminal surface of the internal terminal portion of the circuit member 130 by printing or dispensing, and the circuit member for the semiconductor device of the modified example described above is formed. obtain.

Next, a method for manufacturing the semiconductor device 100 shown in FIG. 1 will be briefly described with reference to FIG.
First, a circuit member 130 shown in FIG. 4 is prepared which is manufactured by external processing as shown in FIG. (6 (a))
Next, the surface on the terminal portion 115 side of the semiconductor element 110 and the surface on the internal terminal portion 131 side of the circuit portion 130 face each other, and the terminal surface 131S of the internal terminal 131 of the circuit portion 130 is formed at the terminal portion 115 of the semiconductor element 110. Are connected via a metal plating layer 138 to electrically connect the terminal portion 115 of the semiconductor element 110 and the internal terminal portion 131 of the circuit portion 130. (Fig. 6 (b))

The terminal part 115 of the semiconductor element 110 and the terminal surface 131S of the internal terminal part 131 of the circuit part 130B are joined by solder reflow, metal eutectic, thermocompression bonding, or the like.
Thereafter, a part of the external terminal portion 132 is exposed to the outside, and the whole is resin-sealed with the sealing resin 150. (Fig. 6 (c))
Further, a surface treatment agent such as solder plating is applied to the exposed terminal surface 132S of the external terminal portion 132, and then external electrodes 170 made of solder balls are formed. (Fig. 6 (d))
Next, each connection lead 134 of the circuit member 130 is cut by pressing, and the outer frame portion 135 is removed. (Fig. 6 (e))
The external electrodes 170 made of solder balls can be manufactured by applying solder paste by screen printing, reflow, or the like, as long as the amount of solder necessary for connection between the circuit board and the semiconductor device is obtained.

(Example)
Furthermore, the present invention will be described with reference to examples of the present invention.
Example 1
In Example 1, the circuit member shown in FIG. 4 was produced by the circuit member manufacturing method shown in FIG. 5 (FIG. 5 (f)), and a metal plating layer for connection was further disposed on the terminal surface of the internal terminal portion. The resin-sealed semiconductor device shown in FIG. 1 is formed by the manufacturing method shown in FIG. 6 using the provided circuit member (FIG. 5G).
First, a circuit member 130a for a semiconductor device shown in FIG. 1 was produced as follows.
This will be described with reference to FIG.
A metal plate 510 made of 42 alloy (Ni 42% Fe alloy) with a thickness of 0.15 mm was prepared, and after degreasing and cleaning (FIG. 5A), both surfaces 510S of the metal plate 510 were placed on Tokyo. A negative resist PMER manufactured by Oka Kogyo Co., Ltd. was applied and dried to form a resist layer 520. (Fig. 5 (b))
Next, the resist layer 520 on the front surface side and the back surface side was exposed through a predetermined pattern plate (photomask), and then developed to form resist patterns 521 and 522, respectively. (Fig. 5 (c))
Next, using the resist patterns 521 and 522 as an etching-resistant mask, spray etching was performed from both surfaces of the metal plate material 510 using a ferric chloride solution (FIGS. 5D and 5E). The resist patterns 521 and 522 were stripped and removed using an alkaline stripping solution, and further subjected to a cleaning treatment or the like, to obtain a circuit member 130 shown in FIG. (Fig. 5 (f))

Next, an electrodeposition resist is formed on the entire surface of the circuit member 130 by electrodeposition, and is exposed and developed through a predetermined pattern plate that matches the metal plating layer region formed on the terminal surface 131S of the internal terminal portion 131. Then, after forming a plating-resistant mask having an opening only in the metal plating layer forming region with an electrodeposition resist, solder plating is performed, and a solder plating layer is formed as an opening in the electrodeposition resist as a metal plating layer for connection. Was removed with a predetermined stripping solution to obtain a circuit member 130a for a semiconductor device shown in FIG. (Fig. 5 (g))
As solder plating, high temperature solder (90% Pb) was used.
The electrodeposition liquid for forming the electrodeposition resist and the stripping liquid for stripping the electrodeposition resist are represented by the Eagle process sold by Shipley.

Next, the internal terminal portion 131 of the circuit member 130 a (FIG. 6A) thus manufactured and the semiconductor element 110 on which the metal bump (terminal 115) is formed are solder-plated to the circuit member 130. After connecting (flip chip connection) through the layer 138 (FIG. 6B), resin sealing was performed. (Fig. 6 (c))
Resin sealing was performed with an epoxy resin using a predetermined mold.
Next, after solder balls are attached to form the external electrodes 170 (FIG. 6D), the connecting leads 134 are cut by a press to be separated from the frame 135, and the resin-encapsulated semiconductor device shown in FIG. Got. (Fig. 6 (e))

(Example 2)
Example 2 is similar to Example 1 except that a circuit member shown in FIG. 4 is produced from a metal plate 510 made of 42 alloy (Ni 42% Fe alloy) having a thickness of 0.15 mm by the method for producing a circuit member shown in FIG. 130 was produced, and furthermore, a circuit member 130a was obtained in which pastes for connection of terminals of semiconductor elements and a connection were formed on the terminal surface of the internal terminal portion of the produced circuit member 130 by a screen printing method. (FIG. 5 (g), FIG. 6 (a)))
As the paste, an Ag—Sn paste was used.
Next, the internal terminal portion 131 of the circuit member 130a thus manufactured (FIG. 6A) and the semiconductor element 110 on which the gold bump (terminal 115) is formed are connected to the paste layer of the circuit member 130a. After being connected (flip-chip connection) via (FIG. 6 (b)), resin sealing was performed. (Fig. 6 (c))
Resin sealing was performed with an epoxy resin using a predetermined mold.
Next, after solder balls are attached to form the external electrodes 170 (FIG. 6D), the connecting leads 134 are cut by a press to be separated from the frame 135, and the resin-encapsulated semiconductor device shown in FIG. Got. (Fig. 6 (e))

100, 101, 102 Resin-sealed semiconductor device 110 Semiconductor element 115 Terminal (pad)
130 circuit member 130A terminal member 130B circuit portion 130S material surface 130a circuit member 131 internal terminal portion 131S (internal terminal portion) terminal surface 132 external terminal portion 132S (external terminal portion) terminal surface 133 lead 134 connection lead 135 frame portion 138 Metal plating layer 150 Sealing resin 170 External electrode 510 made of solder Metal plate material 520 Resist layers 521 and 522 Resist pattern 530 Thin portion

Claims (1)

Mounting on a circuit board or the like on the surface of a resin-encapsulated semiconductor device in which at least a part of the external terminal portion is exposed to the outside and resin-sealed, or the external terminal portion exposed to the outside of the resin-encapsulated semiconductor device A resin-encapsulated semiconductor device provided with external electrodes made of solder for a structure in which flip-chip connection is made to internal terminal portions integrally connected to the external terminals at the terminals of the semiconductor element, and resin encapsulation A CSP (Chip Size Package) whose region is approximately matched to the size of the semiconductor element, and is used when manufacturing a semiconductor device, and is a generally flat circuit member that is electrically connected to the terminals of the semiconductor element. An internal terminal portion, an external terminal portion for connection to an external circuit, and a lead portion that integrally connects the internal terminal portion and the external terminal portion, and the internal terminal portion and the external terminal portion Is the table The internal terminal portion and the lead portion are formed to be thin, the external terminal portion is formed to be thick, and a plurality of terminal members are independent of each other, and the internal terminal portions of each terminal member The outer frame portion that holds the whole by integrally connecting to the external terminal portion via a connection lead different from the lead portion on the outside thereof The plurality of terminal members are connected to the opposing sides of the outer frame portion, and the external terminal portions of the terminal members are connected to the opposing sides of the outer frame portion, respectively. A circuit member is manufactured , which is arranged in two parallel rows along the side of the outer frame portion, and the external terminal portions of the adjacent terminal members are arranged in different rows. A method of manufacturing a circuit member using a metal plate as a raw material, At the same time from the surface side, by selective etching, the internal terminal part, the lead part, and the connection lead part are made to be the material surface, and the external terminal part is made thinner than the thickness of the material by half-etching method. The thickness of the material is processed into an outer shape, and a metal plating layer for flip connection with a semiconductor element is formed on the terminal surface of the internal terminal portion by plating. The metal for flip connection with the semiconductor element The plating layer is formed by coating the entire surface with the photosensitive electrodeposition resist after the outer shape processing, providing a predetermined opening corresponding to the plating region, and plating only the region exposed from the opening using this as a plating mask. A method of manufacturing a circuit member, characterized by applying a partial plating method.

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