JP5506172B2 - 半導体基板の作製方法 - Google Patents

半導体基板の作製方法 Download PDF

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Publication number
JP5506172B2
JP5506172B2 JP2008237942A JP2008237942A JP5506172B2 JP 5506172 B2 JP5506172 B2 JP 5506172B2 JP 2008237942 A JP2008237942 A JP 2008237942A JP 2008237942 A JP2008237942 A JP 2008237942A JP 5506172 B2 JP5506172 B2 JP 5506172B2
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Japan
Prior art keywords
single crystal
film
layer
substrate
crystal semiconductor
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Expired - Fee Related
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JP2008237942A
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English (en)
Japanese (ja)
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JP2009111354A (ja
JP2009111354A5 (enExample
Inventor
舜平 山崎
純一 肥塚
哲弥 掛端
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008237942A priority Critical patent/JP5506172B2/ja
Publication of JP2009111354A publication Critical patent/JP2009111354A/ja
Publication of JP2009111354A5 publication Critical patent/JP2009111354A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2008237942A 2007-10-10 2008-09-17 半導体基板の作製方法 Expired - Fee Related JP5506172B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008237942A JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007264719 2007-10-10
JP2007264719 2007-10-10
JP2008237942A JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009111354A JP2009111354A (ja) 2009-05-21
JP2009111354A5 JP2009111354A5 (enExample) 2011-10-27
JP5506172B2 true JP5506172B2 (ja) 2014-05-28

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Family Applications (1)

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JP2008237942A Expired - Fee Related JP5506172B2 (ja) 2007-10-10 2008-09-17 半導体基板の作製方法

Country Status (3)

Country Link
US (1) US7851332B2 (enExample)
JP (1) JP5506172B2 (enExample)
KR (1) KR101537925B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021033989A1 (ko) * 2019-08-22 2021-02-25 (주)더숨 디스플레이 제조용 기판 및 이의 제조 방법

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JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
TWI437696B (zh) * 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
TWI493609B (zh) * 2007-10-23 2015-07-21 Semiconductor Energy Lab 半導體基板、顯示面板及顯示裝置的製造方法
US8432021B2 (en) * 2009-05-26 2013-04-30 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
US8735191B2 (en) * 2012-01-04 2014-05-27 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding using pedestals
JP5680987B2 (ja) * 2011-02-18 2015-03-04 株式会社アドバンテスト 半導体装置、試験装置、および製造方法
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
WO2013105614A1 (ja) * 2012-01-10 2013-07-18 シャープ株式会社 半導体基板、薄膜トランジスタ、半導体回路、液晶表示装置、エレクトロルミネセンス装置、半導体基板の製造方法、及び半導体基板の製造装置
JP6245791B2 (ja) * 2012-03-27 2017-12-13 日亜化学工業株式会社 縦型窒化物半導体素子およびその製造方法
US9209142B1 (en) 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
KR102407529B1 (ko) * 2015-10-30 2022-06-10 엘지디스플레이 주식회사 플렉서블 표시 장치와 그의 제조 방법
JP6597865B2 (ja) * 2018-10-16 2019-10-30 大日本印刷株式会社 テンプレート基板の製造方法、および、ナノインプリント用テンプレートの製造方法
TWI888525B (zh) * 2020-04-08 2025-07-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法
CN113985219B (zh) * 2021-09-24 2024-05-31 浙江华云电力工程设计咨询有限公司 一种开关柜局部放电和温度联合监测系统及监测方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021033989A1 (ko) * 2019-08-22 2021-02-25 (주)더숨 디스플레이 제조용 기판 및 이의 제조 방법

Also Published As

Publication number Publication date
JP2009111354A (ja) 2009-05-21
KR20090037352A (ko) 2009-04-15
US20090096054A1 (en) 2009-04-16
US7851332B2 (en) 2010-12-14
KR101537925B1 (ko) 2015-07-20

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