JP5500833B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5500833B2
JP5500833B2 JP2009022151A JP2009022151A JP5500833B2 JP 5500833 B2 JP5500833 B2 JP 5500833B2 JP 2009022151 A JP2009022151 A JP 2009022151A JP 2009022151 A JP2009022151 A JP 2009022151A JP 5500833 B2 JP5500833 B2 JP 5500833B2
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Japan
Prior art keywords
oxide film
substrate
film
single crystal
base substrate
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Expired - Fee Related
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JP2009022151A
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English (en)
Japanese (ja)
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JP2009212502A5 (enExample
JP2009212502A (ja
Inventor
英人 大沼
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2009022151A priority Critical patent/JP5500833B2/ja
Publication of JP2009212502A publication Critical patent/JP2009212502A/ja
Publication of JP2009212502A5 publication Critical patent/JP2009212502A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2009022151A 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5500833B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009022151A JP5500833B2 (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008024520 2008-02-04
JP2008024520 2008-02-04
JP2009022151A JP5500833B2 (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009212502A JP2009212502A (ja) 2009-09-17
JP2009212502A5 JP2009212502A5 (enExample) 2012-02-02
JP5500833B2 true JP5500833B2 (ja) 2014-05-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009022151A Expired - Fee Related JP5500833B2 (ja) 2008-02-04 2009-02-03 Ｓｏｉ基板の作製方法

Country Status (4)

Country Link
US (1) US8119490B2 (enExample)
JP (1) JP5500833B2 (enExample)
CN (1) CN101510524B (enExample)
TW (1) TWI494974B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP4333820B1 (ja) * 2009-01-19 2009-09-16 住友電気工業株式会社 化合物半導体基板
WO2011070892A1 (en) * 2009-12-08 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9299852B2 (en) * 2011-06-16 2016-03-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102569501B (zh) * 2011-12-15 2014-06-18 苏州阿特斯阳光电力科技有限公司 一种多晶硅太阳能电池的磷扩散方法
US10103021B2 (en) 2012-01-12 2018-10-16 Shin-Etsu Chemical Co., Ltd. Thermally oxidized heterogeneous composite substrate and method for manufacturing same
TWI645578B (zh) 2012-07-05 2018-12-21 半導體能源研究所股份有限公司 發光裝置及發光裝置的製造方法
KR102173801B1 (ko) 2012-07-12 2020-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치, 및 표시 장치의 제작 방법
CN105448657A (zh) * 2014-09-02 2016-03-30 无锡华润上华半导体有限公司 一种改善高压器件阈值电压均匀性的方法
CN104952791A (zh) * 2015-06-26 2015-09-30 深圳市华星光电技术有限公司 Amoled显示器件的制作方法及其结构
US11289330B2 (en) 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming
CN114188270B (zh) * 2021-12-09 2024-11-22 北京工业大学 一种基于基质面化学反应的固体薄膜剥离方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
KR970052022A (ko) * 1995-12-30 1997-07-29 김주용 에스 오 아이 기판 제조방법
JPH10284431A (ja) * 1997-04-11 1998-10-23 Sharp Corp Ｓｏｉ基板の製造方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
CN1118087C (zh) * 1999-09-27 2003-08-13 中国科学院半导体研究所 一种制备半导体衬底的方法
US6737337B1 (en) * 2001-04-27 2004-05-18 Advanced Micro Devices, Inc. Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7109092B2 (en) * 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
WO2005055293A1 (ja) * 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
FR2868599B1 (fr) * 2004-03-30 2006-07-07 Soitec Silicon On Insulator Traitement chimique optimise de type sc1 pour le nettoyage de plaquettes en materiau semiconducteur
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant

Also Published As

Publication number Publication date
TWI494974B (zh) 2015-08-01
CN101510524A (zh) 2009-08-19
JP2009212502A (ja) 2009-09-17
TW200943387A (en) 2009-10-16
US8119490B2 (en) 2012-02-21
US20090203191A1 (en) 2009-08-13
CN101510524B (zh) 2013-07-24

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