JP5465897B2 - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法 Download PDF

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Publication number
JP5465897B2
JP5465897B2 JP2009051668A JP2009051668A JP5465897B2 JP 5465897 B2 JP5465897 B2 JP 5465897B2 JP 2009051668 A JP2009051668 A JP 2009051668A JP 2009051668 A JP2009051668 A JP 2009051668A JP 5465897 B2 JP5465897 B2 JP 5465897B2
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Japan
Prior art keywords
wafer
wiring
layer
film
integrated circuit
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Expired - Fee Related
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JP2009051668A
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English (en)
Japanese (ja)
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JP2010206058A (ja
JP2010206058A5 (enExample
Inventor
誠 永野
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009051668A priority Critical patent/JP5465897B2/ja
Priority to US12/716,928 priority patent/US8236681B2/en
Publication of JP2010206058A publication Critical patent/JP2010206058A/ja
Publication of JP2010206058A5 publication Critical patent/JP2010206058A5/ja
Application granted granted Critical
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
JP2009051668A 2009-03-05 2009-03-05 半導体集積回路装置の製造方法 Expired - Fee Related JP5465897B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009051668A JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法
US12/716,928 US8236681B2 (en) 2009-03-05 2010-03-03 Manufacturing method of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009051668A JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010206058A JP2010206058A (ja) 2010-09-16
JP2010206058A5 JP2010206058A5 (enExample) 2012-03-29
JP5465897B2 true JP5465897B2 (ja) 2014-04-09

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Family Applications (1)

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JP2009051668A Expired - Fee Related JP5465897B2 (ja) 2009-03-05 2009-03-05 半導体集積回路装置の製造方法

Country Status (2)

Country Link
US (1) US8236681B2 (enExample)
JP (1) JP5465897B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2960700B1 (fr) * 2010-06-01 2012-05-18 Commissariat Energie Atomique Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias
US9887160B2 (en) 2015-09-24 2018-02-06 International Business Machines Corporation Multiple pre-clean processes for interconnect fabrication
KR102616489B1 (ko) 2016-10-11 2023-12-20 삼성전자주식회사 반도체 장치 제조 방법
CN109148356A (zh) * 2017-06-15 2019-01-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US12087692B2 (en) * 2017-09-28 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Hardened interlayer dielectric layer
CN112233977A (zh) * 2020-10-15 2021-01-15 广州粤芯半导体技术有限公司 一种改善晶格损伤的方法
US11990430B2 (en) * 2021-01-28 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structures of integrated circuit devices and method forming the same
CN114400234B (zh) * 2021-12-17 2025-02-25 武汉新芯集成电路股份有限公司 背照式影像传感器芯片及其制作方法
TWI879358B (zh) * 2023-12-29 2025-04-01 慧隆科技股份有限公司 先進半導體裝置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4207285B2 (ja) * 1999-02-10 2009-01-14 ソニー株式会社 半導体装置の製造方法
JP5165817B2 (ja) * 2000-03-31 2013-03-21 ラム リサーチ コーポレーション 静電チャック及びその製造方法
JP2002134489A (ja) * 2000-10-25 2002-05-10 Tokyo Electron Ltd 基板除電方法、気相堆積装置、半導体装置の製造方法
JP4493863B2 (ja) * 2001-01-25 2010-06-30 東京エレクトロン株式会社 プラズマ処理装置およびそのクリーニング方法および静電チャックの除電方法
JP2004014868A (ja) * 2002-06-07 2004-01-15 Tokyo Electron Ltd 静電チャック及び処理装置
JP2004247675A (ja) * 2003-02-17 2004-09-02 Renesas Technology Corp 半導体装置の製造方法
JP2005116801A (ja) * 2003-10-08 2005-04-28 Toshiba Corp 半導体装置の製造方法
US7094705B2 (en) * 2004-01-20 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-step plasma treatment method to improve CU interconnect electrical performance
JP2006165189A (ja) * 2004-12-06 2006-06-22 Nec Electronics Corp 半導体装置の製造方法
JP2007115839A (ja) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及びプラズマ処理装置
JP2007258636A (ja) * 2006-03-27 2007-10-04 Matsushita Electric Ind Co Ltd ドライエッチング方法およびその装置
JP5233097B2 (ja) * 2006-08-15 2013-07-10 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
US7700479B2 (en) * 2006-11-06 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cleaning processes in the formation of integrated circuit interconnect structures
WO2009023100A2 (en) * 2007-08-14 2009-02-19 Skyworks Solutions, Inc. Method for forming a multi-layer electrode underlying a piezoelectric layer and related structure

Also Published As

Publication number Publication date
US20100227470A1 (en) 2010-09-09
JP2010206058A (ja) 2010-09-16
US8236681B2 (en) 2012-08-07

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