JP5427104B2 - パターン形成方法 - Google Patents
パターン形成方法 Download PDFInfo
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- JP5427104B2 JP5427104B2 JP2010109193A JP2010109193A JP5427104B2 JP 5427104 B2 JP5427104 B2 JP 5427104B2 JP 2010109193 A JP2010109193 A JP 2010109193A JP 2010109193 A JP2010109193 A JP 2010109193A JP 5427104 B2 JP5427104 B2 JP 5427104B2
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- pattern
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- resist
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- 238000000034 method Methods 0.000 title claims description 59
- 230000007261 regionalization Effects 0.000 title claims description 7
- 238000011161 development Methods 0.000 claims description 16
- 230000018109 developmental process Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 35
- 239000002184 metal Substances 0.000 description 35
- 239000011229 interlayer Substances 0.000 description 18
- 238000000059 patterning Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
本発明の第1の実施形態に係るパターン形成方法について図1(a)〜図1(e)及び図2(a)〜図2(c)を参照しながら説明する。
以下、本発明の第2の実施形態に係るパターン形成方法について図4(a)〜図4(e)を参照しながら説明する。図4において、図1及び図2に示した構成部材と同一の構成部材には同一の符号を付すことにより説明を省略する。
B 第2の領域(疎な領域)
C 第3の領域(外側領域)
1 基板
2 層間絶縁膜
2a 配線溝パターン
3 ハードマスク形成膜
4 反射防止膜
5A 第1のレジストパターン
5a 第1パターン
5b ダミーパターン
9 第2のレジスト膜
9a 第2パターン
10 第1の開口パターン
11 第2の開口パターン
14a 金属配線
14b 金属配線
50 金属配線パターン
Claims (8)
- 基板の上に、第1のレジスト膜を形成する工程(a)と、
前記第1のレジスト膜に第1の露光光を選択的に照射し、第1の現像を行なうことにより、配線溝パターンを含む第1の領域に第1のパターンを形成すると共に、前記第1の領域と接続され且つ前記配線溝パターンと比べてパターン密度が疎である第2の領域に第1のダミーパターンを形成する工程(b)と、
前記第1のパターン及び第1のダミーパターンが形成された前記第1のレジスト膜を硬化する工程(c)と、
前記工程(c)よりも後に、硬化された前記第1のレジスト膜の上に、第2のレジスト膜を形成する工程(d)と、
前記第2のレジスト膜に第2の露光光を選択的に照射し、第2の現像を行なうことにより、前記第1の領域に第2のパターンを形成する工程(e)とを備え、
前記工程(e)において、前記第1の領域には、前記第1のパターン及び第2のパターンにより前記配線溝パターンを含む開口部が形成される一方、前記第2の領域は、前記第1のダミーパターンの開口部が前記第2のレジスト膜によって埋められ、
前記第1のダミーパターンは、前記第1のダミーパターンの開口部に前記第2のレジスト膜が入り込むことにより、前記第1の領域における前記第2のレジスト膜の膜厚が等しくなる寸法を有することを特徴とするパターン形成方法。 - 前記工程(e)において、前記第2の領域における前記第1のレジスト膜の上に、該第1のレジスト膜を露出する開口部を有する第2のダミーパターンを形成することを特徴とする請求項1に記載のパターン形成方法。
- 前記工程(b)において、前記第2の領域における前記第1のダミーパターンとして、前記第1の領域の外周部に開口部を形成することを特徴とする請求項1又は2に記載のパターン形成方法。
- 前記第1のダミーパターンの開口部は、前記第1のパターンの開口部と接続していることを特徴とする請求項1〜3のいずれか1項に記載のパターン形成方法。
- 前記第2の領域は、前記第2のレジスト膜の塗布膜厚をTとした場合に、前記第1の領域との境界から2Tの距離よりも内側の領域であることを特徴とする請求項1〜4のいずれか1項に記載のパターン形成方法。
- 前記工程(e)において、前記第2のダミーパターンは、前記第2の領域の全体に形成することを特徴とする請求項2に記載のパターン形成方法。
- 前記工程(b)において、前記第1のダミーパターンの開口率は、前記第1のパターンの開口率の±20%以内であることを特徴とする請求項5に記載のパターン形成方法。
- 前記第1のダミーパターン及び第2のダミーパターンの少なくとも一方は、前記第2の領域の外側の第3の領域に形成されていることを特徴とする請求項2に記載のパターン形成方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010109193A JP5427104B2 (ja) | 2010-05-11 | 2010-05-11 | パターン形成方法 |
US13/010,355 US8445184B2 (en) | 2010-05-11 | 2011-01-20 | Pattern formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010109193A JP5427104B2 (ja) | 2010-05-11 | 2010-05-11 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011238782A JP2011238782A (ja) | 2011-11-24 |
JP5427104B2 true JP5427104B2 (ja) | 2014-02-26 |
Family
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JP2010109193A Expired - Fee Related JP5427104B2 (ja) | 2010-05-11 | 2010-05-11 | パターン形成方法 |
Country Status (2)
Country | Link |
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US (1) | US8445184B2 (ja) |
JP (1) | JP5427104B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130006794A (ko) * | 2011-06-23 | 2013-01-18 | 삼성전자주식회사 | 미세 패턴 형성 방법 및 반도체 소자의 제조 방법 |
US8765612B2 (en) * | 2012-09-14 | 2014-07-01 | Nanya Technology Corporation | Double patterning process |
US10283437B2 (en) * | 2012-11-27 | 2019-05-07 | Advanced Micro Devices, Inc. | Metal density distribution for double pattern lithography |
JP2015046459A (ja) * | 2013-08-28 | 2015-03-12 | ソニー株式会社 | エッチング方法、電子デバイスの製造方法および偏光板の製造方法 |
CN103489769B (zh) * | 2013-09-22 | 2016-09-07 | 上海华力微电子有限公司 | 制作高均匀度栅极线条的方法 |
CN103474337B (zh) * | 2013-09-22 | 2016-02-03 | 上海华力微电子有限公司 | 制作栅极线条的方法 |
US9263349B2 (en) * | 2013-11-08 | 2016-02-16 | Globalfoundries Inc. | Printing minimum width semiconductor features at non-minimum pitch and resulting device |
US9606432B2 (en) * | 2014-11-05 | 2017-03-28 | GlobalFoundries, Inc. | Alternating space decomposition in circuit structure fabrication |
WO2016134309A1 (en) * | 2015-02-21 | 2016-08-25 | Tokyo Electron Limited | Method for patterning incorporating misalignment error protection |
KR102410139B1 (ko) | 2015-09-04 | 2022-06-16 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
CN108946656A (zh) * | 2017-05-25 | 2018-12-07 | 联华电子股份有限公司 | 半导体制作工艺 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2919004B2 (ja) * | 1990-07-12 | 1999-07-12 | 沖電気工業株式会社 | パターン形成方法 |
US5667940A (en) * | 1994-05-11 | 1997-09-16 | United Microelectronics Corporation | Process for creating high density integrated circuits utilizing double coating photoresist mask |
JP3311244B2 (ja) * | 1996-07-15 | 2002-08-05 | 株式会社東芝 | 基本セルライブラリ及びその形成方法 |
JP2003303824A (ja) * | 2002-04-12 | 2003-10-24 | Sony Corp | 半導体装置の製造方法 |
JP4480424B2 (ja) * | 2004-03-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | パターン形成方法 |
US7271083B2 (en) * | 2004-07-22 | 2007-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-transistor random access memory technology compatible with metal gate process |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
KR100752674B1 (ko) | 2006-10-17 | 2007-08-29 | 삼성전자주식회사 | 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법 |
JP5035562B2 (ja) * | 2007-08-22 | 2012-09-26 | 信越化学工業株式会社 | パターン形成方法 |
WO2009044434A1 (ja) * | 2007-10-05 | 2009-04-09 | Fujitsu Microelectronics Limited | 半導体装置の製造方法、露光用マスク製造方法、及びその製造に用いられるプログラム |
US7935477B2 (en) * | 2007-11-30 | 2011-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning strategy for contact hole and trench |
KR101435520B1 (ko) * | 2008-08-11 | 2014-09-01 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
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2010
- 2010-05-11 JP JP2010109193A patent/JP5427104B2/ja not_active Expired - Fee Related
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2011
- 2011-01-20 US US13/010,355 patent/US8445184B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US8445184B2 (en) | 2013-05-21 |
JP2011238782A (ja) | 2011-11-24 |
US20110281220A1 (en) | 2011-11-17 |
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