CN108946656A - 半导体制作工艺 - Google Patents

半导体制作工艺 Download PDF

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Publication number
CN108946656A
CN108946656A CN201710377577.8A CN201710377577A CN108946656A CN 108946656 A CN108946656 A CN 108946656A CN 201710377577 A CN201710377577 A CN 201710377577A CN 108946656 A CN108946656 A CN 108946656A
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manufacture craft
fabrication process
semiconductor fabrication
process according
chip
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魏国智
陈翁宜
李世伟
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201710377577.8A priority Critical patent/CN108946656A/zh
Priority to US15/644,430 priority patent/US20180339901A1/en
Publication of CN108946656A publication Critical patent/CN108946656A/zh
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    • B81C1/00801—Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer
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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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Abstract

本发明公开一种半导体制作工艺，包括以下步骤。提供晶片，其中晶片具有正面与背面，且在晶片的正面上具有半导体元件。在晶片的正面上形成保护层，其中保护层覆盖半导体元件，且保护层的材料包括光致抗蚀剂材料。对保护层进行表面硬化处理制作工艺。对晶片的背面进行第一图案化制作工艺。上述半导体制作工艺在进行晶背制作工艺时可有效地对晶片的正面进行保护。上述半导体制作工艺在进行晶背制作工艺时可有效地对晶片的正面进行保护。

Description

半导体制作工艺
技术领域
本发明涉及一种半导体制作工艺，且特别是涉及一种在进行晶背制作工艺(backside process)时对晶片的正面进行保护的半导体制作工艺。
背景技术
目前，在对晶片的背面进行图案化制作工艺来形成开口(如，空腔(cavity)或穿孔(through hole))时，业界常使用光致抗蚀剂材料作为保护层来保护晶片的正面。然而，若光致抗蚀剂材料的保护性不佳，仍会对晶片正面的半导体元件造成伤害。
因此，目前业界提出一种使用PIQ(日立化成工业股份有限公司制(HITACHICHEMICAL CO.,LTD.))的聚酰亚胺(polyimide)树脂作为晶片正面的保护层。PIQ树脂虽然在进行干蚀刻制作工艺时可具有较佳的保护效果，但PIQ树脂在进行湿蚀刻时容易因剥离而失去保护效果。
发明内容
为解决上述问题，本发明提出一种半导体制作工艺，其在进行晶背制作工艺时可有效地对晶片的正面进行保护。
本发明提供一种半导体制作工艺，包括以下步骤。提供晶片，其中晶片具有正面与背面，且在晶片的正面上具有半导体元件。在晶片的正面上形成保护层，其中保护层覆盖半导体元件，且保护层的材料包括光致抗蚀剂材料。对保护层进行表面硬化处理制作工艺。对晶片的背面进行第一图案化制作工艺。
依照本发明的一实施例所述，在上述半导体制作工艺中，半导体元件例如是微机电系统(microelectromechanical system，MEMS)元件或逻辑元件。
依照本发明的一实施例所述，在上述半导体制作工艺中，微机电系统元件例如是感测器元件。
依照本发明的一实施例所述，在上述半导体制作工艺中，感测器元件例如是加速度计、微机电系统麦克风(MEMS microphone)、光感测器或气体感测器。
依照本发明的一实施例所述，在上述半导体制作工艺中，还包括在形成保护层之前或之后，对晶片的背面进行薄化制作工艺(thinning process)。
依照本发明的一实施例所述，在上述半导体制作工艺中，薄化制作工艺例如是研磨制作工艺(grinding process)。
依照本发明的一实施例所述，在上述半导体制作工艺中，光致抗蚀剂材料例如是I-线(I-line)光致抗蚀剂、氟化氩(ArF)光致抗蚀剂或氟化氪(KrF)光致抗蚀剂。
依照本发明的一实施例所述，在上述半导体制作工艺中，还包括在进行表面硬化处理制作工艺之前，对保护层进行第二图案化制作工艺。
依照本发明的一实施例所述，在上述半导体制作工艺中，第二图案化制作工艺例如是光刻制作工艺。
依照本发明的一实施例所述，在上述半导体制作工艺中，表面硬化处理制作工艺包括对保护层进行离子注入制作工艺。
依照本发明的一实施例所述，在上述半导体制作工艺中，其中离子注入制作工艺的掺质例如是磷、硼或砷。
依照本发明的一实施例所述，在上述半导体制作工艺中，离子注入制作工艺的注入浓度例如是1×1015离子/平方厘米至4×1015离子/平方厘米。
依照本发明的一实施例所述，在上述半导体制作工艺中，离子注入制作工艺的注入能量例如是50keV至100keV。
依照本发明的一实施例所述，在上述半导体制作工艺中，还包括在进行离子注入制作工艺之前，对保护层进行回火制作工艺(anneal process)。
依照本发明的一实施例所述，在上述半导体制作工艺中，回火制作工艺的温度例如是150℃至250℃。
依照本发明的一实施例所述，在上述半导体制作工艺中，第一图案化制作工艺包括以下步骤。在晶片的背面上形成图案化光致抗蚀剂层。以图案化光致抗蚀剂层作为掩模，从晶片的背面移除部分晶片。
依照本发明的一实施例所述，在上述半导体制作工艺中，部分晶片的移除方法例如是干蚀刻制作工艺、湿蚀刻制作工艺或其组合。
依照本发明的一实施例所述，在上述半导体制作工艺中，干蚀刻制作工艺例如是深反应性离子蚀刻(deep reactive ion etching，DRIE)制作工艺。
依照本发明的一实施例所述，在上述半导体制作工艺中，还包括在移除部分晶片之后，移除图案化光致抗蚀剂层。
依照本发明的一实施例所述，在上述半导体制作工艺中，还包括在进行第一图案化制作工艺之后，移除保护层。
基于上述，在本发明所提出的半导体制作工艺中，由于对保护层进行表面硬化处理制作工艺，因此在对晶片的背面进行图案化制作工艺时，经表面硬化处理的保护层可有效地对晶片的正面进行保护，以防止位于晶片的正面上的半导体元件受到伤害，进而可提升半导体元件的可靠度与良率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1为本发明一实施例的半导体制作工艺的流程图；
图2A至图2G为本发明一实施例的半导体制造流程的剖视图。
符号说明：
100：晶片
100a：硅基底
100b：硅层
100c：绝缘层
102：半导体元件
102a：悬臂梁
102b：感测质量块
104：保护层
106、110：开口
108：图案化光致抗蚀剂层
200：回火制作工艺
202：离子注入制作工艺
S1：正面
S2：背面
S100、S102、S104、S106、S108、S108a、S108b、S110、S112：步骤
具体实施方式
图1为本发明一实施例的半导体制作工艺的流程图。图2A至图2G为本发明一实施例的半导体制造流程的剖视图。
请同时参照图1与图2A，进行步骤S100，提供晶片100，其中晶片100具有正面S1与背面S2，且在晶片100的正面S1上具有半导体元件102。晶片100可为半导体晶片或绝缘层上有硅的(silicon-on-insulator，SOI)晶片。在此实施例中，晶片100是以SOI晶片为例来进行说明，但本发明并不以此为限。举例来说，晶片100可包括硅基底100a、硅层100b与绝缘层100c，其中绝缘层100c设置于硅基底100a与硅层100b之间。绝缘层100c的材料例如是氧化硅。
半导体元件102例如是微机电系统元件或逻辑元件。微机电系统元件例如是感测器元件，如加速度计、微机电系统麦克风、光感测器或气体感测器等。在此实施例中，半导体元件102是以微机电系统元件中的加速度计为例来进行说明，但本发明并不以此为限。举例来说，当半导体元件102为加速度计时，半导体元件102包括悬臂梁(beam)102a与感测质量块(proof mass)102b。
可选择性地进行步骤S102，对晶片100的背面S2进行薄化制作工艺，以移除部分晶片100。举例来说，可移除晶片100的部分硅基底100a。薄化制作工艺例如是研磨制作工艺。
进行步骤S104，在晶片100的正面S1上形成保护层104，其中保护层104覆盖半导体元件102，且保护层104的材料包括光致抗蚀剂材料。光致抗蚀剂材料例如是I-线(I-line)光致抗蚀剂、氟化氩(ArF)光致抗蚀剂或氟化氪(KrF)光致抗蚀剂。I-线(I-line)光致抗蚀剂、氟化氩(ArF)光致抗蚀剂与氟化氪(KrF)光致抗蚀剂分别为可对I-线(I-line)光源(波长为365nm)、氟化氩(ArF)气体激光(波长为193nm)与氟化氪(KrF)气体激光(波长为248nm)进行感光的光致抗蚀剂材料。
在此实施例中，是以在形成保护层104(步骤S104)之前，对晶片100的背面S2进行薄化制作工艺(步骤S102)为例来进行说明，但本发明并不以此为限。在另一实施例中，也可在形成保护层104之后，再对晶片100的背面S2进行薄化制作工艺。亦即，可先进行步骤S104(形成保护层104)，再进行步骤S102(薄化制作工艺)。
请同时参照图1与图2B，可选择性地进行步骤S106，对保护层104进行图案化制作工艺。为了特定制作工艺需求，可通过图案化制作工艺在保护层104中形成开口106。图案化制作工艺例如是光刻制作工艺。在其他实施例中，也可省略步骤S106。
请同时参照图1、图2C与图2D，进行步骤S108，对保护层104进行表面硬化处理制作工艺，以使得保护层104的表面硬化，而具有较佳的保护效果。
步骤S108的表面硬化处理制作工艺包括步骤S108b(离子注入制作工艺)。此外，在进行步骤S108b之前，步骤S108的表面硬化处理制作工艺更可选择性地包括步骤S108a(回火制作工艺)。
在此实施例中，步骤S108的表面硬化处理制作工艺举例说明如下。请同时参照图1与图2C，可选择性地进行步骤S108a，对保护层104进行回火制作工艺200。回火制作工艺有助于保护层104的表面硬化。回火制作工艺的温度例如是150℃至250℃。在一实施例中，回火制作工艺的温度可为约200℃。
请同时参照图1与图2D，进行步骤S108b，对保护层104进行离子注入制作工艺202，以将保护层104的表面硬化。为了使保护层104具有所需的表面刚性(surface stiffness)，所注入的掺质需与选定的注入浓度与注入能量做搭配，举例说明如下。原子量大的掺质(如，磷(P))需搭配较大的注入能量，原子量小的掺质(如，硼(B))需搭配较小的注入能量，以使得掺质分布在表层。离子注入制作工艺的掺质例如是磷、硼或砷。离子注入制作工艺的注入浓度例如是1×1015离子/平方厘米至4×1015离子/平方厘米(ions/cm2)。离子注入制作工艺的注入能量例如是50keV至100keV。在一实施例中，离子注入制作工艺的注入浓度可为2.25×1015离子/平方厘米，且离子注入制作工艺的注入能量可为70keV。
之后，请同时参照图1、图2E至图2G，进行步骤S110，对晶片100的背面S2进行图案化制作工艺，以在晶片100的背面S2形成所需的开口110。开口110例如是空腔(cavity)或穿孔(through hole)。
以下，通过图2E至图2G来说明步骤S110的图案化制作工艺。
请参照图2E，在晶片100的背面S2上形成图案化光致抗蚀剂层108。图案化光致抗蚀剂层108的材料例如是I-线(I-line)光致抗蚀剂、氟化氩(ArF)光致抗蚀剂或氟化氪(KrF)光致抗蚀剂。图案化光致抗蚀剂层108例如是通过光刻制作工艺所形成。
请同时参照图2E与图2F，以图案化光致抗蚀剂层108作为掩模，从晶片100的背面S2移除部分晶片100，以在晶片100中形成开口110。部分晶片100的移除方法例如是干蚀刻制作工艺、湿蚀刻制作工艺或其组合。
举例来说，请参照图2E，可利用图案化光致抗蚀剂层108作为掩模，通过干蚀刻制作工艺从晶片100的背面S2移除由图案化光致抗蚀剂层108所暴露的部分硅基底100a，而形成开口110。干蚀刻制作工艺例如是深反应性离子蚀刻(DRIE)制作工艺。接着，请参照图2F，可选择性地移除由图案化光致抗蚀剂层108所暴露的绝缘层100c。详细来说，可利用图案化光致抗蚀剂层108作为掩模，通过湿蚀刻制作工艺或干蚀刻制作工艺从晶片100的背面S2移除由图案化光致抗蚀剂层108所暴露的绝缘层100c。此时，开口110与开口106可相互连通。湿蚀刻制作工艺所使用的蚀刻剂例如是氢氟酸(HF)或缓冲氧化物蚀刻剂(buffered oxideetchant，BOE)。
接下来，请参照图2G，移除图案化光致抗蚀剂层108。图案化光致抗蚀剂层108的移除方法例如是干式去光致抗蚀剂法(dry stripping)或湿式去光致抗蚀剂法(wetstripping)。
请同时参照图1与图2G，可选择性地进行步骤S112，移除保护层104。保护层104的移除方法例如是干式去光致抗蚀剂法(dry stripping)或湿式去光致抗蚀剂法(wetstripping)。保护层104与图案化光致抗蚀剂层108的移除顺序并没有一定的顺序。在保护层104与图案化光致抗蚀剂层108的成分相同时，可通过同一道移除制作工艺同时移除保护层104与图案化光致抗蚀剂层108，由此可进一步地降低制作工艺复杂度。此外，在保护层104与图案化光致抗蚀剂层108的成分不同时，可先移除图案化光致抗蚀剂层108，再移除保护层104，或者可先移除保护层104，再移除图案化光致抗蚀剂层108。
基于上述实施例可知，由于对保护层104进行表面硬化处理制作工艺，因此在对晶片100的背面S2进行图案化制作工艺时，经表面硬化处理的保护层104可有效地对晶片100的正面S1进行保护。因此，不论对晶片100的背面S2所进行图案化制作工艺是使用干蚀刻制作工艺或湿蚀刻制作工艺，通过保护层104均可防止位于晶片100的正面S1上的半导体元件102受到伤害，进而可提升半导体元件102的可靠度与良率。
综上所述，在上述实施例的半导体制作工艺中，在进行晶背制作工艺时，通过经表面硬化处理的保护层可有效地对晶片的正面进行保护，进而可提升半导体元件的可靠度与良率。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种半导体制作工艺，其特征在于，包括：
提供晶片，其中所述晶片具有正面与背面，且在所述晶片的所述正面上具有半导体元件；
在所述晶片的所述正面上形成保护层，其中所述保护层覆盖所述半导体元件，且所述保护层的材料包括光致抗蚀剂材料；
对所述保护层进行表面硬化处理制作工艺；以及
对所述晶片的所述背面进行第一图案化制作工艺。
2.根据权利要求1所述的半导体制作工艺，其特征在于，所述半导体元件包括微机电系统元件或逻辑元件。
3.根据权利要求2所述的半导体制作工艺，其特征在于，所述微机电系统元件包括感测器元件。
4.根据权利要求3所述的半导体制作工艺，其特征在于，所述感测器元件包括加速度计、微机电系统麦克风、光感测器或气体感测器。
5.根据权利要求1所述的半导体制作工艺，其特征在于，还包括在形成所述保护层之前或之后，对所述晶片的所述背面进行薄化制作工艺。
6.根据权利要求5所述的半导体制作工艺，其特征在于，所述薄化制作工艺包括研磨制作工艺。
7.根据权利要求1所述的半导体制作工艺，其特征在于，所述光致抗蚀剂材料包括I-线光致抗蚀剂、氟化氩光致抗蚀剂或氟化氪光致抗蚀剂。
8.根据权利要求1所述的半导体制作工艺，其特征在于，还包括在进行所述表面硬化处理制作工艺之前，对所述保护层进行第二图案化制作工艺。
9.根据权利要求8所述的半导体制作工艺，其特征在于，所述第二图案化制作工艺包括光刻制作工艺。
10.根据权利要求1所述的半导体制作工艺，其特征在于，所述表面硬化处理制作工艺包括对所述保护层进行离子注入制作工艺。
11.根据权利要求10所述的半导体制作工艺，其特征在于，所述离子注入制作工艺的掺质包括磷、硼或砷。
12.根据权利要求10所述的半导体制作工艺，其特征在于，所述离子注入制作工艺的注入浓度为1×1015离子/平方厘米至4×1015离子/平方厘米。
13.根据权利要求10所述的半导体制作工艺，其特征在于，所述离子注入制作工艺的注入能量为50keV至100keV。
14.根据权利要求10所述的半导体制作工艺，其特征在于，还包括在进行所述离子注入制作工艺之前，对所述保护层进行回火制作工艺。
15.根据权利要求14所述的半导体制作工艺，其特征在于，所述回火制作工艺的温度为150℃至250℃。
16.根据权利要求1所述的半导体制作工艺，其特征在于，所述第一图案化制作工艺包括：
在所述晶片的所述背面上形成图案化光致抗蚀剂层；以及
以所述图案化光致抗蚀剂层作为掩模，从所述晶片的所述背面移除部分所述晶片。
17.根据权利要求16所述的半导体制作工艺，其特征在于，部分所述晶片的移除方法包括干蚀刻制作工艺、湿蚀刻制作工艺或其组合。
18.根据权利要求17所述的半导体制作工艺，其特征在于，所述干蚀刻制作工艺包括深反应性离子蚀刻制作工艺。
19.根据权利要求16所述的半导体制作工艺，其特征在于，还包括在移除部分所述晶片之后，移除所述图案化光致抗蚀剂层。
20.根据权利要求1所述的半导体制作工艺，其特征在于，还包括在进行所述第一图案化制作工艺之后，移除所述保护层。
CN201710377577.8A 2017-05-25 2017-05-25 半导体制作工艺 Pending CN108946656A (zh)

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