JP5415766B2 - 逆t型チャネルトランジスタを製造する方法 - Google Patents
逆t型チャネルトランジスタを製造する方法 Download PDFInfo
- Publication number
- JP5415766B2 JP5415766B2 JP2008537752A JP2008537752A JP5415766B2 JP 5415766 B2 JP5415766 B2 JP 5415766B2 JP 2008537752 A JP2008537752 A JP 2008537752A JP 2008537752 A JP2008537752 A JP 2008537752A JP 5415766 B2 JP5415766 B2 JP 5415766B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- horizontal
- activation
- activation region
- fin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/36—Unipolar devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/257,973 | 2005-10-25 | ||
| US11/257,973 US8513066B2 (en) | 2005-10-25 | 2005-10-25 | Method of making an inverted-T channel transistor |
| PCT/US2006/040019 WO2007050317A2 (en) | 2005-10-25 | 2006-10-11 | A method of making an inverted-t channel transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009514220A JP2009514220A (ja) | 2009-04-02 |
| JP2009514220A5 JP2009514220A5 (enExample) | 2009-12-03 |
| JP5415766B2 true JP5415766B2 (ja) | 2014-02-12 |
Family
ID=37968343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008537752A Expired - Fee Related JP5415766B2 (ja) | 2005-10-25 | 2006-10-11 | 逆t型チャネルトランジスタを製造する方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8513066B2 (enExample) |
| EP (1) | EP1943680A2 (enExample) |
| JP (1) | JP5415766B2 (enExample) |
| KR (1) | KR20080069971A (enExample) |
| CN (1) | CN101297406A (enExample) |
| TW (1) | TW200721324A (enExample) |
| WO (1) | WO2007050317A2 (enExample) |
Families Citing this family (67)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| US7579280B2 (en) * | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
| US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
| US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
| US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
| US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
| US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
| US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
| US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
| US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
| US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
| US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
| US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
| US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
| US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
| US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
| US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
| US7968394B2 (en) * | 2005-12-16 | 2011-06-28 | Freescale Semiconductor, Inc. | Transistor with immersed contacts and methods of forming thereof |
| US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
| US7723805B2 (en) * | 2006-01-10 | 2010-05-25 | Freescale Semiconductor, Inc. | Electronic device including a fin-type transistor structure and a process for forming the electronic device |
| US7754560B2 (en) * | 2006-01-10 | 2010-07-13 | Freescale Semiconductor, Inc. | Integrated circuit using FinFETs and having a static random access memory (SRAM) |
| US7709303B2 (en) * | 2006-01-10 | 2010-05-04 | Freescale Semiconductor, Inc. | Process for forming an electronic device including a fin-type structure |
| US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
| US20090001426A1 (en) * | 2007-06-29 | 2009-01-01 | Kangguo Cheng | Integrated Fin-Local Interconnect Structure |
| WO2009044236A1 (en) | 2007-10-03 | 2009-04-09 | Freescale Semiconductor, Inc. | Method of forming an inverted t shaped channel structure for an inverted t channel field effect transistor device |
| ES2489615T3 (es) * | 2007-12-11 | 2014-09-02 | Apoteknos Para La Piel, S.L. | Uso de un compuesto derivado del acido p-hidroxifenil propionico para el tratamiento de la psoriasis |
| US7923328B2 (en) * | 2008-04-15 | 2011-04-12 | Freescale Semiconductor, Inc. | Split gate non-volatile memory cell with improved endurance and method therefor |
| JP2009283685A (ja) * | 2008-05-22 | 2009-12-03 | Panasonic Corp | 半導体装置およびその製造方法 |
| US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
| US8305829B2 (en) * | 2009-02-23 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
| US8305790B2 (en) * | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
| US8957482B2 (en) * | 2009-03-31 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
| US8912602B2 (en) * | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
| US8461015B2 (en) * | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
| US8472227B2 (en) * | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
| US8264021B2 (en) * | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
| US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
| US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
| US8623728B2 (en) | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
| US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
| US8482073B2 (en) * | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
| US8980719B2 (en) | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
| US8759943B2 (en) * | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
| US8298925B2 (en) | 2010-11-08 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
| US8629478B2 (en) * | 2009-07-31 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure for high mobility multiple-gate transistor |
| US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
| US20110097867A1 (en) * | 2009-10-22 | 2011-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of controlling gate thicknesses in forming fusi gates |
| US9040393B2 (en) | 2010-01-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
| CN102263131B (zh) * | 2010-05-25 | 2013-05-01 | 中国科学院微电子研究所 | 一种半导体器件及其形成方法 |
| US8603924B2 (en) | 2010-10-19 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming gate dielectric material |
| US9048181B2 (en) | 2010-11-08 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
| US8769446B2 (en) | 2010-11-12 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for increasing fin device density for unaligned fins |
| US8592915B2 (en) | 2011-01-25 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doped oxide for shallow trench isolation (STI) |
| US8877602B2 (en) | 2011-01-25 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of doping oxide for forming shallow trench isolation |
| US8431453B2 (en) | 2011-03-31 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure |
| CN103390637B (zh) * | 2012-05-09 | 2016-01-13 | 中国科学院微电子研究所 | FinFET及其制造方法 |
| US8673704B2 (en) | 2012-05-09 | 2014-03-18 | Institute of Microelectronics, Chinese Academy of Sciences | FinFET and method for manufacturing the same |
| US8956932B2 (en) | 2013-02-25 | 2015-02-17 | International Business Machines Corporation | U-shaped semiconductor structure |
| CN104103506B (zh) * | 2013-04-11 | 2018-02-13 | 中国科学院微电子研究所 | 半导体器件制造方法 |
| CN103400858B (zh) * | 2013-08-02 | 2016-01-20 | 清华大学 | 绝缘体上三维半导体器件及其形成方法 |
| JP2015053477A (ja) * | 2013-08-05 | 2015-03-19 | 株式会社半導体エネルギー研究所 | 半導体装置および半導体装置の作製方法 |
| CN104425601B (zh) * | 2013-08-30 | 2018-02-16 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| US10615161B2 (en) | 2016-02-08 | 2020-04-07 | International Business Machines Corporation | III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface |
| CN110943130B (zh) * | 2018-09-20 | 2024-08-23 | 长鑫存储技术有限公司 | 晶体管、半导体存储器及其制造方法 |
| CN116593561B (zh) * | 2023-03-23 | 2025-12-16 | 西安电子科技大学 | 基于倒t形负电容隧穿场效应晶体管的生物传感器及制备方法 |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5738731A (en) * | 1993-11-19 | 1998-04-14 | Mega Chips Corporation | Photovoltaic device |
| JP2571004B2 (ja) * | 1993-12-22 | 1997-01-16 | 日本電気株式会社 | 薄膜トランジスタ |
| KR0144165B1 (ko) * | 1995-05-12 | 1998-07-01 | 문정환 | 인버스 티(t)형 트랜지스터의 개선된 제조방법 |
| US7052941B2 (en) * | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
| KR100268895B1 (ko) * | 1997-12-27 | 2000-10-16 | 김영환 | 박막트랜지스터 및 이의 제조방법 |
| US6034417A (en) * | 1998-05-08 | 2000-03-07 | Micron Technology, Inc. | Semiconductor structure having more usable substrate area and method for forming same |
| US20020036347A1 (en) * | 1998-10-28 | 2002-03-28 | Theodore W Houston | Local interconnect structures and methods |
| JP4270719B2 (ja) * | 1999-06-30 | 2009-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6630712B2 (en) * | 1999-08-11 | 2003-10-07 | Advanced Micro Devices, Inc. | Transistor with dynamic source/drain extensions |
| US6252284B1 (en) * | 1999-12-09 | 2001-06-26 | International Business Machines Corporation | Planarized silicon fin device |
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
| US20040059703A1 (en) * | 2002-09-23 | 2004-03-25 | Jerry Chappell | Cascading behavior of package generation/installation based on variable parameters |
| US6864519B2 (en) * | 2002-11-26 | 2005-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS SRAM cell configured using multiple-gate transistors |
| JP2004214413A (ja) * | 2002-12-27 | 2004-07-29 | Toshiba Corp | 半導体装置 |
| JP2005005465A (ja) * | 2003-06-11 | 2005-01-06 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
| US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
| US6909147B2 (en) * | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
| US7192876B2 (en) * | 2003-05-22 | 2007-03-20 | Freescale Semiconductor, Inc. | Transistor with independent gate structures |
| US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
| KR100496891B1 (ko) * | 2003-08-14 | 2005-06-23 | 삼성전자주식회사 | 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법 |
| CN100546042C (zh) * | 2003-12-08 | 2009-09-30 | 国际商业机器公司 | 具有增加的节点电容的半导体存储器件 |
| US7388258B2 (en) | 2003-12-10 | 2008-06-17 | International Business Machines Corporation | Sectional field effect devices |
| US7385247B2 (en) * | 2004-01-17 | 2008-06-10 | Samsung Electronics Co., Ltd. | At least penta-sided-channel type of FinFET transistor |
| US7060539B2 (en) * | 2004-03-01 | 2006-06-13 | International Business Machines Corporation | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby |
| KR100549008B1 (ko) * | 2004-03-17 | 2006-02-02 | 삼성전자주식회사 | 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법 |
| WO2005094254A2 (en) * | 2004-03-17 | 2005-10-13 | The Board Of Trustees Of The Leland Stanford Junior University | Crystalline-type device and approach therefor |
| KR100541054B1 (ko) * | 2004-03-23 | 2006-01-11 | 삼성전자주식회사 | 하드마스크 스페이서를 채택하여 3차원 모오스 전계효과트랜지스터를 제조하는 방법 |
| US7098477B2 (en) * | 2004-04-23 | 2006-08-29 | International Business Machines Corporation | Structure and method of manufacturing a finFET device having stacked fins |
| US7122412B2 (en) * | 2004-04-30 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a necked FINFET device |
| US6972461B1 (en) * | 2004-06-30 | 2005-12-06 | International Business Machines Corporation | Channel MOSFET with strained silicon channel on strained SiGe |
| US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
| US7589387B2 (en) * | 2005-10-05 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | SONOS type two-bit FinFET flash memory cell |
| KR100653711B1 (ko) * | 2005-11-14 | 2006-12-05 | 삼성전자주식회사 | 쇼트키 배리어 핀 펫 소자 및 그 제조방법 |
| US7564081B2 (en) * | 2005-11-30 | 2009-07-21 | International Business Machines Corporation | finFET structure with multiply stressed gate electrode |
-
2005
- 2005-10-25 US US11/257,973 patent/US8513066B2/en active Active
-
2006
- 2006-10-11 EP EP06825883A patent/EP1943680A2/en not_active Withdrawn
- 2006-10-11 WO PCT/US2006/040019 patent/WO2007050317A2/en not_active Ceased
- 2006-10-11 KR KR1020087009898A patent/KR20080069971A/ko not_active Withdrawn
- 2006-10-11 JP JP2008537752A patent/JP5415766B2/ja not_active Expired - Fee Related
- 2006-10-11 CN CNA2006800397325A patent/CN101297406A/zh active Pending
- 2006-10-17 TW TW095138266A patent/TW200721324A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007050317A3 (en) | 2007-06-21 |
| CN101297406A (zh) | 2008-10-29 |
| TW200721324A (en) | 2007-06-01 |
| US8513066B2 (en) | 2013-08-20 |
| KR20080069971A (ko) | 2008-07-29 |
| US20070093010A1 (en) | 2007-04-26 |
| EP1943680A2 (en) | 2008-07-16 |
| WO2007050317A2 (en) | 2007-05-03 |
| JP2009514220A (ja) | 2009-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5415766B2 (ja) | 逆t型チャネルトランジスタを製造する方法 | |
| US8643066B2 (en) | Multiple device types including an inverted-T channel transistor and method therefor | |
| CN111128882B (zh) | 集成电路器件及其形成方法 | |
| US7422946B2 (en) | Independently accessed double-gate and tri-gate transistors in same process flow | |
| US7018551B2 (en) | Pull-back method of forming fins in FinFets | |
| US8609480B2 (en) | Methods of forming isolation structures on FinFET semiconductor devices | |
| TWI339406B (en) | Locally thinned fins | |
| US20070114612A1 (en) | Method of fabricating semiconductor devices having MCFET/finFET and related device | |
| US20050062088A1 (en) | Multi-gate one-transistor dynamic random access memory | |
| US7859044B2 (en) | Partially gated FINFET with gate dielectric on only one sidewall | |
| KR20050091190A (ko) | 핀 전계 효과 트랜지스터 및 그 제조방법 | |
| TW201637099A (zh) | 半導體裝置的製造方法 | |
| JP2007501524A (ja) | 全体的な設計目標を達成すべく、半導体デバイス中のキャリア移動度の可変な半導体デバイス | |
| US20220367725A1 (en) | Multi-gate device and related methods | |
| TW202027231A (zh) | 製造半導體裝置的方法 | |
| TWI767417B (zh) | 半導體裝置及其製造方法 | |
| JP2008028357A (ja) | 半導体素子及びその製造方法 | |
| TW201935690A (zh) | 半導體裝置的布局、半導體裝置及其形成方法 | |
| TWI637510B (zh) | 具有放大通道區的finfet裝置 | |
| US20240387518A1 (en) | Capacitor in nanosheet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091013 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091013 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120919 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120920 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121220 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130509 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130809 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131016 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131114 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5415766 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |