JP5383501B2 - 低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い - Google Patents

低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い Download PDF

Info

Publication number
JP5383501B2
JP5383501B2 JP2009541642A JP2009541642A JP5383501B2 JP 5383501 B2 JP5383501 B2 JP 5383501B2 JP 2009541642 A JP2009541642 A JP 2009541642A JP 2009541642 A JP2009541642 A JP 2009541642A JP 5383501 B2 JP5383501 B2 JP 5383501B2
Authority
JP
Japan
Prior art keywords
layer
exposing
plasma
implanted
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009541642A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010514166A (ja
JP2010514166A5 (enExample
Inventor
マジード エー． フォード，
マノージ ヴェライカル，
カルティク サンタナム，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of JP2010514166A publication Critical patent/JP2010514166A/ja
Publication of JP2010514166A5 publication Critical patent/JP2010514166A5/ja
Application granted granted Critical
Publication of JP5383501B2 publication Critical patent/JP5383501B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/94—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
    • H10P32/1204—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase from a plasma phase

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Physical Vapour Deposition (AREA)
JP2009541642A 2006-12-18 2007-12-18 低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い Expired - Fee Related JP5383501B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US87057506P 2006-12-18 2006-12-18
US60/870,575 2006-12-18
PCT/US2007/087894 WO2008077020A2 (en) 2006-12-18 2007-12-18 Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers

Publications (3)

Publication Number Publication Date
JP2010514166A JP2010514166A (ja) 2010-04-30
JP2010514166A5 JP2010514166A5 (enExample) 2010-12-09
JP5383501B2 true JP5383501B2 (ja) 2014-01-08

Family

ID=39537046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009541642A Expired - Fee Related JP5383501B2 (ja) 2006-12-18 2007-12-18 低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い

Country Status (6)

Country Link
US (3) US20080153271A1 (enExample)
JP (1) JP5383501B2 (enExample)
KR (1) KR101369993B1 (enExample)
CN (1) CN101548190A (enExample)
TW (1) TWI508142B (enExample)
WO (1) WO2008077020A2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8118946B2 (en) * 2007-11-30 2012-02-21 Wesley George Lau Cleaning process residues from substrate processing chamber components
JP2012507867A (ja) * 2008-10-31 2012-03-29 アプライド マテリアルズ インコーポレイテッド Ｐ３ｉプロセスにおけるドーピングプロファイルの調整
US7858503B2 (en) * 2009-02-06 2010-12-28 Applied Materials, Inc. Ion implanted substrate having capping layer and method
TW201205648A (en) * 2010-06-23 2012-02-01 Tokyo Electron Ltd Plasma doping device, plasma doping method, method for manufacturing semiconductor element, and semiconductor element
US8501605B2 (en) * 2011-03-14 2013-08-06 Applied Materials, Inc. Methods and apparatus for conformal doping
US20120289036A1 (en) * 2011-05-11 2012-11-15 Applied Materials, Inc. Surface dose retention of dopants by pre-amorphization and post implant passivation treatments
WO2013164940A1 (ja) * 2012-05-01 2013-11-07 東京エレクトロン株式会社 被処理基体にドーパントを注入する方法、及びプラズマドーピング装置
EP3149011A4 (en) 2014-05-30 2018-06-13 Dow Corning Corporation Process of synthesizing diisopropylaminw-disilanes
FR3033079B1 (fr) * 2015-02-19 2018-04-27 Ion Beam Services Procede de passivation d'un substrat et machine pour la mise en oeuvre de ce procede
WO2018052471A1 (en) * 2016-09-14 2018-03-22 Applied Materials, Inc. A degassing chamber for arsenic related processes
US11501972B2 (en) * 2020-07-22 2022-11-15 Applied Materials, Inc. Sacrificial capping layer for passivation using plasma-based implant process
US12494251B2 (en) * 2022-08-26 2025-12-09 Micron Technology, Inc. Memory circuitry and method used in forming memory circuitry

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4226667A (en) * 1978-10-31 1980-10-07 Bell Telephone Laboratories, Incorporated Oxide masking of gallium arsenide
JP3103629B2 (ja) * 1990-11-08 2000-10-30 松下電子工業株式会社 砒化化合物半導体装置の製造方法
US5196370A (en) * 1990-11-08 1993-03-23 Matsushita Electronics Corporation Method of manufacturing an arsenic-including compound semiconductor device
US6039851A (en) * 1995-03-22 2000-03-21 Micron Technology, Inc. Reactive sputter faceting of silicon dioxide to enhance gap fill of spaces between metal lines
JPH1131665A (ja) * 1997-07-11 1999-02-02 Hitachi Ltd 半導体集積回路装置の製造方法
KR100271043B1 (ko) * 1997-11-28 2000-11-01 구본준, 론 위라하디락사 액정표시장치의 기판 및 그 제조방법(liquid crystal display and method of manufacturing the same)
EP0932191A1 (en) * 1997-12-30 1999-07-28 International Business Machines Corporation Method of plasma etching doped polysilicon layers with uniform etch rates
US6376285B1 (en) * 1998-05-28 2002-04-23 Texas Instruments Incorporated Annealed porous silicon with epitaxial layer for SOI
US6239034B1 (en) * 1998-11-02 2001-05-29 Vanguard International Semiconductor Corporation Method of manufacturing inter-metal dielectric layers for semiconductor devices
US20020033233A1 (en) * 1999-06-08 2002-03-21 Stephen E. Savas Icp reactor having a conically-shaped plasma-generating section
JP2001085392A (ja) * 1999-09-10 2001-03-30 Toshiba Corp 半導体装置の製造方法
US6586318B1 (en) * 1999-12-28 2003-07-01 Xerox Corporation Thin phosphorus nitride film as an N-type doping source used in laser doping technology
US7037813B2 (en) * 2000-08-11 2006-05-02 Applied Materials, Inc. Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage
US7064399B2 (en) * 2000-09-15 2006-06-20 Texas Instruments Incorporated Advanced CMOS using super steep retrograde wells
US6613695B2 (en) * 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US6566283B1 (en) * 2001-02-15 2003-05-20 Advanced Micro Devices, Inc. Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
KR100428769B1 (ko) * 2001-06-22 2004-04-28 삼성전자주식회사 반도체 롬 장치 형성 방법
JP4151884B2 (ja) * 2001-08-08 2008-09-17 独立行政法人理化学研究所 固体表面に複合金属酸化物のナノ材料が形成された材料の製造方法
US7003111B2 (en) * 2001-10-11 2006-02-21 International Business Machines Corporation Method, system, and program, for encoding and decoding input data
JP3578345B2 (ja) * 2002-03-27 2004-10-20 株式会社半導体先端テクノロジーズ 半導体装置の製造方法および半導体装置
JP4001498B2 (ja) * 2002-03-29 2007-10-31 東京エレクトロン株式会社 絶縁膜の形成方法及び絶縁膜の形成システム
US6743651B2 (en) * 2002-04-23 2004-06-01 International Business Machines Corporation Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen
US20040072446A1 (en) * 2002-07-02 2004-04-15 Applied Materials, Inc. Method for fabricating an ultra shallow junction of a field effect transistor
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
US20050205986A1 (en) * 2004-03-18 2005-09-22 Ikuroh Ichitsubo Module with integrated active substrate and passive substrate
US20060011906A1 (en) * 2004-07-14 2006-01-19 International Business Machines Corporation Ion implantation for suppression of defects in annealed SiGe layers
US7037818B2 (en) * 2004-08-20 2006-05-02 International Business Machines Corporation Apparatus and method for staircase raised source/drain structure
US7141457B2 (en) * 2004-11-18 2006-11-28 International Business Machines Corporation Method to form Si-containing SOI and underlying substrate with different orientations
US20060205192A1 (en) * 2005-03-09 2006-09-14 Varian Semiconductor Equipment Associates, Inc. Shallow-junction fabrication in semiconductor devices via plasma implantation and deposition
US7504314B2 (en) * 2005-04-06 2009-03-17 International Business Machines Corporation Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom

Also Published As

Publication number Publication date
JP2010514166A (ja) 2010-04-30
TWI508142B (zh) 2015-11-11
US20080153271A1 (en) 2008-06-26
KR101369993B1 (ko) 2014-03-06
US8927400B2 (en) 2015-01-06
TW200834681A (en) 2008-08-16
US20100173484A1 (en) 2010-07-08
WO2008077020A3 (en) 2008-08-28
KR20090100421A (ko) 2009-09-23
WO2008077020A2 (en) 2008-06-26
CN101548190A (zh) 2009-09-30
US20140248759A1 (en) 2014-09-04

Similar Documents

Publication Publication Date Title
JP5383501B2 (ja) 低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い
US7989329B2 (en) Removal of surface dopants from a substrate
KR102384484B1 (ko) 펄싱된 플라즈마 노출을 사용하여 플라즈마 강화된 원자층 증착
US8084105B2 (en) Method of depositing boron nitride and boron nitride-derived materials
US9478415B2 (en) Method for forming film having low resistance and shallow junction depth
US20140273530A1 (en) Post-Deposition Treatment Methods For Silicon Nitride
KR101244850B1 (ko) 인장 응력 및 압축 응력을 받은 반도체용 재료
JP5331703B2 (ja) プラズマ浸漬イオン注入プロセス
KR20180073483A (ko) 기판 상의 구조물 형성 방법
US20140273524A1 (en) Plasma Doping Of Silicon-Containing Films
KR20120057570A (ko) 프로세스 챔버벽들 상의 실리콘 코팅을 사용하는 잔여 불소 라디칼들의 강화된 스캐빈징
TW202317808A (zh) 在反應空間中在基板上形成氮化矽薄膜的方法
JP2010510677A (ja) ゲートスタック構造の順次処理のクラスター化方法
KR102691504B1 (ko) 펄스형 플라즈마 증착 에칭 스텝 커버리지 개선
US8288257B2 (en) Doping profile modification in P3I process
KR20210109046A (ko) 질화규소를 증착하는 방법들
JP2012525014A (ja) 側部ガス出口を有する基板支持体および方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101018

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101018

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20101130

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101210

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20120925

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130305

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130605

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130612

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130729

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130910

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131001

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees