JP5383501B2 - 低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い - Google Patents
低エネルギーの高用量ヒ素、リン、ホウ素注入ウエハの安全な取り扱い Download PDFInfo
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Description
[0001]本発明の実施形態は、一般的には、半導体製造プロセスの分野に関し、より具体的には、ヒ素、リン、又はホウ素で注入された基板の取り扱いをより安全にする方法に関する。
[0002]集積回路は、基板(例えば、半導体ウエハ)上に形成される百万を超えるマイクロ電界効果型トランジスタ(例えば、相補型金属酸化半導体(CMOS)電界効果型トランジスタ)を含み、回路内で様々な機能を行うように協調することができるものである。CMOSトランジスタは、基板内に形成されるソース領域とドレイン領域の間に配置されるゲート構造を備えている。ゲート構造は、一般に、ゲート電極とゲート誘電体層を備えている。ゲート電極は、ゲート誘電体層の下のドレイン領域とソース領域の間に形成されるチャンネル領域において荷電キャリアの流れを制御するようにゲート誘電体層の上に配置される。
(I) R2NSi(R'2)Si(R'2)NR2(アミノジシラン)、
(II) R3SiN3(シリルアジド)、又は
(III)R'3SiNRNR2(シリルヒドラジン)
[0038]上記化学式において、RとR’はハロゲン、一つ以上の二重結合を有する有機基、一つ以上の三重結合を有する有機基、脂肪族アルキル基、環状アルキル基、芳香族基、有機シリル基、アルキルアミノ基、又はN或いはSiを含有する環状基、又はこれらの組み合わせの群より独立して選ばれる一つ以上の官能基であってもよい。特定の官能基には、、クロロ(-Cl)、メチル(-CH3)、エチル(-CH2CH3)、イソプロピル(-CH(CH3)2)、tertブチル(-C(CH3)3)、トリメチルシリル(-Si(CH3)3)、ピロリジン、又はこれらの組み合わせが含まれる。
Claims (11)
- 基板処理方法であって、
処理チャンバ内に配置される膜にドーパントを注入するステップと、
注入された該膜を酸素含有プラズマにさらして、注入された該膜上に酸化物層を形成すると共に注入された該膜を大気中の酸素にさらす前に該膜中に該ドーパントをトラップするステップと、
注入された該膜を該酸素含有プラズマと別に水素含有プラズマにさらすステップと、
を含む、方法。 - 該ドーパントが、ヒ素、リン、ホウ素、及びこれらの組み合わせからなる群より選ばれる、請求項1に記載の方法。
- 該酸素含有プラズマが、酸素ガスから生成される、請求項2に記載の方法。
- 注入する該ステップとさらす該ステップが、同一処理チャンバ内で行われる、請求項3に記載の方法。
- 該プラズマが、容量結合ソースによって生成され、該プラズマが該容量結合ソースに加えて誘導結合プラズマソースによって生成される、請求項4に記載の方法。
- 該プラズマが、誘導結合ソースによって生成される、請求項4記載の方法。
- 注入された該膜を水素含有プラズマにさらす該ステップが、注入する該ステップ後と酸素含有プラズマにさらす該ステップ前に行われ、水素含有プラズマにさらす該ステップと酸素含有プラズマにさらす該ステップが、複数回行われる、請求項1に記載の方法。
- 注入された該膜を水素含有プラズマにさらす該ステップが、注入する該ステップ後と酸素含有プラズマにさらす該ステップ後に行われ、水素含有プラズマにさらす該ステップと酸素含有プラズマにさらす該ステップが、複数回行われる、請求項1に記載の方法。
- 該酸化物層の上にキャッピング層を堆積させるステップであって、該キャッピング層が、炭素層、シリコン層、酸化シリコン層、窒化シリコン層、炭化シリコン層、有機層、及びこれらの組み合わせからなる群より選ばれる、前記ステップを更に含み、注入する該ステップ後であってさらす該ステップの前に該膜をエッチングするステップであって、余分なドーパントを除去し、注入された該層をNF3から形成されるプラズマにさらす工程を含む、前記ステップを更に含む、請求項1に記載の方法。
- 基板処理方法であって、
処理チャンバ内の基板上に配置される膜にドーパントを注入するステップと、
注入された該膜が大気中の酸素にさらされる前に該ドーパントの注入された膜の上にキャッピング層を堆積させるステップであって、該キャッピング層が、炭素層、シリコン層、酸化シリコン層、窒化シリコン層、炭化シリコン層、有機層、及びこれらの組み合わせからなる群より選ばれる、前記ステップと、
注入する該ステップ後であって堆積させる該ステップ前に該膜をエッチングするステップであって、余分なドーパントを除去し、注入された該層をNF3から形成されるプラズマにさらす工程を含む、前記ステップと、
を含む、方法。 - 注入する該ステップと堆積させる該ステップが、同一処理チャンバ内で行われる、請求項10に記載の方法。
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US87057506P | 2006-12-18 | 2006-12-18 | |
US60/870,575 | 2006-12-18 | ||
PCT/US2007/087894 WO2008077020A2 (en) | 2006-12-18 | 2007-12-18 | Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers |
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JP2010514166A JP2010514166A (ja) | 2010-04-30 |
JP2010514166A5 JP2010514166A5 (ja) | 2010-12-09 |
JP5383501B2 true JP5383501B2 (ja) | 2014-01-08 |
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US (3) | US20080153271A1 (ja) |
JP (1) | JP5383501B2 (ja) |
KR (1) | KR101369993B1 (ja) |
CN (1) | CN101548190A (ja) |
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WO (1) | WO2008077020A2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8118946B2 (en) * | 2007-11-30 | 2012-02-21 | Wesley George Lau | Cleaning process residues from substrate processing chamber components |
US8288257B2 (en) * | 2008-10-31 | 2012-10-16 | Applied Materials, Inc. | Doping profile modification in P3I process |
US7858503B2 (en) * | 2009-02-06 | 2010-12-28 | Applied Materials, Inc. | Ion implanted substrate having capping layer and method |
JP2013534712A (ja) * | 2010-06-23 | 2013-09-05 | 東京エレクトロン株式会社 | プラズマドーピング装置、プラズマドーピング方法、半導体素子の製造方法、および半導体素子 |
US8501605B2 (en) * | 2011-03-14 | 2013-08-06 | Applied Materials, Inc. | Methods and apparatus for conformal doping |
TW201246305A (en) * | 2011-05-11 | 2012-11-16 | Applied Materials Inc | Surface dose retention of dopants by pre-amorphization and post-implant passivation treatments |
WO2013164940A1 (ja) * | 2012-05-01 | 2013-11-07 | 東京エレクトロン株式会社 | 被処理基体にドーパントを注入する方法、及びプラズマドーピング装置 |
KR102065329B1 (ko) | 2014-05-30 | 2020-01-13 | 다우 실리콘즈 코포레이션 | 다이아이소프로필아미노-다이실란의 합성 공정 |
FR3033079B1 (fr) * | 2015-02-19 | 2018-04-27 | Ion Beam Services | Procede de passivation d'un substrat et machine pour la mise en oeuvre de ce procede |
EP3513426A4 (en) * | 2016-09-14 | 2020-06-10 | Applied Materials, Inc. | DEGASSING CHAMBER FOR ARSENIC ASSOCIATED PROCESSES |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4226667A (en) * | 1978-10-31 | 1980-10-07 | Bell Telephone Laboratories, Incorporated | Oxide masking of gallium arsenide |
JP3103629B2 (ja) * | 1990-11-08 | 2000-10-30 | 松下電子工業株式会社 | 砒化化合物半導体装置の製造方法 |
US5196370A (en) * | 1990-11-08 | 1993-03-23 | Matsushita Electronics Corporation | Method of manufacturing an arsenic-including compound semiconductor device |
US6039851A (en) * | 1995-03-22 | 2000-03-21 | Micron Technology, Inc. | Reactive sputter faceting of silicon dioxide to enhance gap fill of spaces between metal lines |
JPH1131665A (ja) * | 1997-07-11 | 1999-02-02 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
KR100271043B1 (ko) * | 1997-11-28 | 2000-11-01 | 구본준, 론 위라하디락사 | 액정표시장치의 기판 및 그 제조방법(liquid crystal display and method of manufacturing the same) |
EP0932191A1 (en) * | 1997-12-30 | 1999-07-28 | International Business Machines Corporation | Method of plasma etching doped polysilicon layers with uniform etch rates |
US6376285B1 (en) * | 1998-05-28 | 2002-04-23 | Texas Instruments Incorporated | Annealed porous silicon with epitaxial layer for SOI |
US6239034B1 (en) * | 1998-11-02 | 2001-05-29 | Vanguard International Semiconductor Corporation | Method of manufacturing inter-metal dielectric layers for semiconductor devices |
US20020033233A1 (en) * | 1999-06-08 | 2002-03-21 | Stephen E. Savas | Icp reactor having a conically-shaped plasma-generating section |
JP2001085392A (ja) * | 1999-09-10 | 2001-03-30 | Toshiba Corp | 半導体装置の製造方法 |
US6586318B1 (en) * | 1999-12-28 | 2003-07-01 | Xerox Corporation | Thin phosphorus nitride film as an N-type doping source used in laser doping technology |
US7037813B2 (en) * | 2000-08-11 | 2006-05-02 | Applied Materials, Inc. | Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage |
US7064399B2 (en) * | 2000-09-15 | 2006-06-20 | Texas Instruments Incorporated | Advanced CMOS using super steep retrograde wells |
US6613695B2 (en) * | 2000-11-24 | 2003-09-02 | Asm America, Inc. | Surface preparation prior to deposition |
US6566283B1 (en) * | 2001-02-15 | 2003-05-20 | Advanced Micro Devices, Inc. | Silane treatment of low dielectric constant materials in semiconductor device manufacturing |
US6855436B2 (en) * | 2003-05-30 | 2005-02-15 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
KR100428769B1 (ko) * | 2001-06-22 | 2004-04-28 | 삼성전자주식회사 | 반도체 롬 장치 형성 방법 |
JP4151884B2 (ja) * | 2001-08-08 | 2008-09-17 | 独立行政法人理化学研究所 | 固体表面に複合金属酸化物のナノ材料が形成された材料の製造方法 |
US7003111B2 (en) * | 2001-10-11 | 2006-02-21 | International Business Machines Corporation | Method, system, and program, for encoding and decoding input data |
JP3578345B2 (ja) * | 2002-03-27 | 2004-10-20 | 株式会社半導体先端テクノロジーズ | 半導体装置の製造方法および半導体装置 |
JP4001498B2 (ja) * | 2002-03-29 | 2007-10-31 | 東京エレクトロン株式会社 | 絶縁膜の形成方法及び絶縁膜の形成システム |
US6743651B2 (en) * | 2002-04-23 | 2004-06-01 | International Business Machines Corporation | Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen |
WO2004006303A2 (en) * | 2002-07-02 | 2004-01-15 | Applied Materials, Inc. | Method for fabricating an ultra shallow junction of a field effect transistor |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US20050205986A1 (en) * | 2004-03-18 | 2005-09-22 | Ikuroh Ichitsubo | Module with integrated active substrate and passive substrate |
US20060011906A1 (en) * | 2004-07-14 | 2006-01-19 | International Business Machines Corporation | Ion implantation for suppression of defects in annealed SiGe layers |
US7037818B2 (en) * | 2004-08-20 | 2006-05-02 | International Business Machines Corporation | Apparatus and method for staircase raised source/drain structure |
US7141457B2 (en) * | 2004-11-18 | 2006-11-28 | International Business Machines Corporation | Method to form Si-containing SOI and underlying substrate with different orientations |
US20060205192A1 (en) * | 2005-03-09 | 2006-09-14 | Varian Semiconductor Equipment Associates, Inc. | Shallow-junction fabrication in semiconductor devices via plasma implantation and deposition |
US7504314B2 (en) * | 2005-04-06 | 2009-03-17 | International Business Machines Corporation | Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom |
-
2007
- 2007-12-18 CN CNA2007800445412A patent/CN101548190A/zh active Pending
- 2007-12-18 WO PCT/US2007/087894 patent/WO2008077020A2/en active Application Filing
- 2007-12-18 US US11/958,541 patent/US20080153271A1/en not_active Abandoned
- 2007-12-18 KR KR1020097015192A patent/KR101369993B1/ko active IP Right Grant
- 2007-12-18 JP JP2009541642A patent/JP5383501B2/ja not_active Expired - Fee Related
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2010
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Also Published As
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US20080153271A1 (en) | 2008-06-26 |
TW200834681A (en) | 2008-08-16 |
US8927400B2 (en) | 2015-01-06 |
US20140248759A1 (en) | 2014-09-04 |
JP2010514166A (ja) | 2010-04-30 |
TWI508142B (zh) | 2015-11-11 |
CN101548190A (zh) | 2009-09-30 |
KR101369993B1 (ko) | 2014-03-06 |
KR20090100421A (ko) | 2009-09-23 |
WO2008077020A3 (en) | 2008-08-28 |
WO2008077020A2 (en) | 2008-06-26 |
US20100173484A1 (en) | 2010-07-08 |
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