JP5362985B2 - 空隙を有する半導体デバイスの形成方法および該方法によって形成された構造 - Google Patents
空隙を有する半導体デバイスの形成方法および該方法によって形成された構造 Download PDFInfo
- Publication number
- JP5362985B2 JP5362985B2 JP2007515228A JP2007515228A JP5362985B2 JP 5362985 B2 JP5362985 B2 JP 5362985B2 JP 2007515228 A JP2007515228 A JP 2007515228A JP 2007515228 A JP2007515228 A JP 2007515228A JP 5362985 B2 JP5362985 B2 JP 5362985B2
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- Prior art keywords
- metal wiring
- wiring level
- trench
- dielectric material
- conductive material
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/709722 | 2004-05-25 | ||
| US10/709,722 US7078814B2 (en) | 2004-05-25 | 2004-05-25 | Method of forming a semiconductor device having air gaps and the structure so formed |
| PCT/US2005/018050 WO2005117085A2 (en) | 2004-05-25 | 2005-05-23 | Gap-type conductive interconnect structures in semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008502140A JP2008502140A (ja) | 2008-01-24 |
| JP2008502140A5 JP2008502140A5 (enExample) | 2008-05-15 |
| JP5362985B2 true JP5362985B2 (ja) | 2013-12-11 |
Family
ID=35451549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007515228A Expired - Fee Related JP5362985B2 (ja) | 2004-05-25 | 2005-05-23 | 空隙を有する半導体デバイスの形成方法および該方法によって形成された構造 |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US7078814B2 (enExample) |
| EP (1) | EP1766670A4 (enExample) |
| JP (1) | JP5362985B2 (enExample) |
| KR (1) | KR100956718B1 (enExample) |
| CN (1) | CN1954414A (enExample) |
| TW (1) | TW200539382A (enExample) |
| WO (1) | WO2005117085A2 (enExample) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291298B1 (en) | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| US7229499B2 (en) * | 2003-08-22 | 2007-06-12 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer |
| US7071091B2 (en) * | 2004-04-20 | 2006-07-04 | Intel Corporation | Method of forming air gaps in a dielectric material using a sacrificial film |
| US7629225B2 (en) * | 2005-06-13 | 2009-12-08 | Infineon Technologies Ag | Methods of manufacturing semiconductor devices and structures thereof |
| US7732322B2 (en) * | 2006-02-23 | 2010-06-08 | International Business Machines Corporation | Dielectric material with reduced dielectric constant and methods of manufacturing the same |
| JP4827639B2 (ja) * | 2006-07-12 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7482261B2 (en) * | 2006-07-26 | 2009-01-27 | International Business Machines Corporation | Interconnect structure for BEOL applications |
| TWI321819B (en) * | 2006-11-27 | 2010-03-11 | Innolux Display Corp | Metal line damascene structure and fabricating method for the same |
| US7485567B2 (en) * | 2007-02-02 | 2009-02-03 | International Business Machines Corporation | Microelectronic circuit structure with layered low dielectric constant regions and method of forming same |
| US20080185722A1 (en) * | 2007-02-05 | 2008-08-07 | Chung-Shi Liu | Formation process of interconnect structures with air-gaps and sidewall spacers |
| JP2008205283A (ja) * | 2007-02-21 | 2008-09-04 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置の配線構造並びにその設計方法及び設計装置 |
| US7544602B2 (en) * | 2007-03-29 | 2009-06-09 | International Business Machines Corporation | Method and structure for ultra narrow crack stop for multilevel semiconductor device |
| JP5342189B2 (ja) * | 2008-08-06 | 2013-11-13 | 株式会社日立製作所 | 不揮発性記憶装置及びその製造方法 |
| US8138036B2 (en) * | 2008-08-08 | 2012-03-20 | International Business Machines Corporation | Through silicon via and method of fabricating same |
| KR101536333B1 (ko) * | 2009-03-26 | 2015-07-14 | 삼성전자주식회사 | 배선 구조물 및 이의 형성 방법 |
| US8298911B2 (en) * | 2009-03-26 | 2012-10-30 | Samsung Electronics Co., Ltd. | Methods of forming wiring structures |
| WO2011021244A1 (ja) * | 2009-08-20 | 2011-02-24 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US8003516B2 (en) * | 2009-08-26 | 2011-08-23 | International Business Machines Corporation | BEOL interconnect structures and related fabrication methods |
| US8456009B2 (en) * | 2010-02-18 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having an air-gap region and a method of manufacturing the same |
| KR20120048991A (ko) * | 2010-11-08 | 2012-05-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| CN103021929A (zh) * | 2011-09-22 | 2013-04-03 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件制造方法 |
| KR101827893B1 (ko) | 2012-02-22 | 2018-02-09 | 삼성전자주식회사 | 도전 라인 구조물 및 그 형성 방법 |
| US8900989B2 (en) | 2013-03-06 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating an air gap using a damascene process and structure of same |
| CN105518837B (zh) * | 2013-09-27 | 2019-04-16 | 英特尔公司 | 用于后段(beol)互连的自对准过孔及插塞图案化 |
| US9853025B1 (en) * | 2016-10-14 | 2017-12-26 | International Business Machines Corporation | Thin film metallic resistors formed by surface treatment of insulating layer |
| US11004612B2 (en) * | 2019-03-14 | 2021-05-11 | MicroSol Technologies Inc. | Low temperature sub-nanometer periodic stack dielectrics |
| KR102590870B1 (ko) * | 2020-04-10 | 2023-10-19 | 주식회사 히타치하이테크 | 에칭 방법 |
| KR102845535B1 (ko) * | 2021-04-06 | 2025-08-13 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
| US12444613B2 (en) | 2022-02-14 | 2025-10-14 | Hitachi High-Tech Corporation | Etching processing method |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05283542A (ja) * | 1992-03-31 | 1993-10-29 | Mitsubishi Electric Corp | 半導体集積回路装置及びその製造方法 |
| US5470801A (en) * | 1993-06-28 | 1995-11-28 | Lsi Logic Corporation | Low dielectric constant insulation layer for integrated circuit structure and method of making same |
| US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
| US5548159A (en) * | 1994-05-27 | 1996-08-20 | Texas Instruments Incorporated | Porous insulator for line-to-line capacitance reduction |
| JPH09275142A (ja) * | 1995-12-12 | 1997-10-21 | Texas Instr Inc <Ti> | 半導体の空隙を低温低圧で充填を行う処理方法 |
| US5994776A (en) * | 1996-01-11 | 1999-11-30 | Advanced Micro Devices, Inc. | Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit |
| US5965202A (en) * | 1996-05-02 | 1999-10-12 | Lucent Technologies, Inc. | Hybrid inorganic-organic composite for use as an interlayer dielectric |
| WO2004074355A1 (ja) * | 1997-05-28 | 2004-09-02 | Noriko Yamada | 低誘電率材料、 その製造および使用 |
| US6577011B1 (en) * | 1997-07-10 | 2003-06-10 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| JP3571522B2 (ja) * | 1998-02-12 | 2004-09-29 | 松下電器産業株式会社 | 多孔質膜の形成方法及び多孔質膜の形成材料 |
| JP4521992B2 (ja) * | 1998-04-01 | 2010-08-11 | 旭化成株式会社 | 配線構造体の製造方法 |
| US6265780B1 (en) * | 1998-12-01 | 2001-07-24 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
| US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
| JP3888794B2 (ja) * | 1999-01-27 | 2007-03-07 | 松下電器産業株式会社 | 多孔質膜の形成方法、配線構造体及びその形成方法 |
| US6177329B1 (en) * | 1999-04-15 | 2001-01-23 | Kurt Pang | Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets |
| US6090698A (en) * | 1999-07-23 | 2000-07-18 | United Microelectronics Corp | Fabrication method for an insulation structure having a low dielectric constant |
| US6596624B1 (en) * | 1999-07-31 | 2003-07-22 | International Business Machines Corporation | Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier |
| US6103619A (en) * | 1999-10-08 | 2000-08-15 | United Microelectronics Corp. | Method of forming a dual damascene structure on a semiconductor wafer |
| JP2001118842A (ja) * | 1999-10-15 | 2001-04-27 | Nec Corp | 半導体装置とその製造方法 |
| US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
| US6297554B1 (en) * | 2000-03-10 | 2001-10-02 | United Microelectronics Corp. | Dual damascene interconnect structure with reduced parasitic capacitance |
| US6362091B1 (en) * | 2000-03-14 | 2002-03-26 | Intel Corporation | Method for making a semiconductor device having a low-k dielectric layer |
| US6265321B1 (en) * | 2000-04-17 | 2001-07-24 | Chartered Semiconductor Manufacturing Ltd. | Air bridge process for forming air gaps |
| US6287979B1 (en) * | 2000-04-17 | 2001-09-11 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer |
| US6413852B1 (en) * | 2000-08-31 | 2002-07-02 | International Business Machines Corporation | Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material |
| WO2002023629A2 (en) * | 2000-09-13 | 2002-03-21 | Shipley Company, L.L.C. | Electronic device manufacture |
| TW465039B (en) * | 2000-11-06 | 2001-11-21 | United Microelectronics Corp | Void-type metal interconnect and method for making the same |
| US6603204B2 (en) * | 2001-02-28 | 2003-08-05 | International Business Machines Corporation | Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
| US6448177B1 (en) * | 2001-03-27 | 2002-09-10 | Intle Corporation | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure |
| US6933586B2 (en) * | 2001-12-13 | 2005-08-23 | International Business Machines Corporation | Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens |
| JP2003289099A (ja) * | 2002-03-27 | 2003-10-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
| FR2851373B1 (fr) * | 2003-02-18 | 2006-01-13 | St Microelectronics Sa | Procede de fabrication d'un circuit electronique integre incorporant des cavites |
-
2004
- 2004-05-25 US US10/709,722 patent/US7078814B2/en not_active Expired - Lifetime
-
2005
- 2005-05-04 TW TW094114443A patent/TW200539382A/zh unknown
- 2005-05-23 KR KR1020067022307A patent/KR100956718B1/ko not_active Expired - Fee Related
- 2005-05-23 WO PCT/US2005/018050 patent/WO2005117085A2/en not_active Ceased
- 2005-05-23 EP EP05751777A patent/EP1766670A4/en not_active Withdrawn
- 2005-05-23 JP JP2007515228A patent/JP5362985B2/ja not_active Expired - Fee Related
- 2005-05-23 CN CNA2005800153631A patent/CN1954414A/zh active Pending
-
2006
- 2006-03-28 US US11/391,050 patent/US7459389B2/en not_active Expired - Fee Related
-
2008
- 2008-08-29 US US12/201,266 patent/US7674705B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7459389B2 (en) | 2008-12-02 |
| US7078814B2 (en) | 2006-07-18 |
| EP1766670A4 (en) | 2011-03-02 |
| US20090008788A1 (en) | 2009-01-08 |
| US7674705B2 (en) | 2010-03-09 |
| WO2005117085A2 (en) | 2005-12-08 |
| KR100956718B1 (ko) | 2010-05-06 |
| WO2005117085A3 (en) | 2006-10-12 |
| CN1954414A (zh) | 2007-04-25 |
| JP2008502140A (ja) | 2008-01-24 |
| US20050275104A1 (en) | 2005-12-15 |
| EP1766670A2 (en) | 2007-03-28 |
| KR20070021191A (ko) | 2007-02-22 |
| TW200539382A (en) | 2005-12-01 |
| US20060166486A1 (en) | 2006-07-27 |
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