JP5353892B2 - アラインメント装置およびアラインメント方法 - Google Patents

アラインメント装置およびアラインメント方法 Download PDF

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Publication number
JP5353892B2
JP5353892B2 JP2010531752A JP2010531752A JP5353892B2 JP 5353892 B2 JP5353892 B2 JP 5353892B2 JP 2010531752 A JP2010531752 A JP 2010531752A JP 2010531752 A JP2010531752 A JP 2010531752A JP 5353892 B2 JP5353892 B2 JP 5353892B2
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stage
microscope
alignment
substrate
unit
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JP2010531752A
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English (en)
Japanese (ja)
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JPWO2010038454A1 (ja
Inventor
崇広 堀越
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Nikon Corp
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Nikon Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2010531752A 2008-10-01 2009-09-30 アラインメント装置およびアラインメント方法 Active JP5353892B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010531752A JP5353892B2 (ja) 2008-10-01 2009-09-30 アラインメント装置およびアラインメント方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008256803 2008-10-01
JP2008256803 2008-10-01
PCT/JP2009/005048 WO2010038454A1 (ja) 2008-10-01 2009-09-30 アラインメント装置およびアラインメント方法
JP2010531752A JP5353892B2 (ja) 2008-10-01 2009-09-30 アラインメント装置およびアラインメント方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013169208A Division JP2014013916A (ja) 2008-10-01 2013-08-16 アラインメント装置およびアラインメント方法

Publications (2)

Publication Number Publication Date
JPWO2010038454A1 JPWO2010038454A1 (ja) 2012-03-01
JP5353892B2 true JP5353892B2 (ja) 2013-11-27

Family

ID=42073234

Family Applications (2)

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JP2010531752A Active JP5353892B2 (ja) 2008-10-01 2009-09-30 アラインメント装置およびアラインメント方法
JP2013169208A Withdrawn JP2014013916A (ja) 2008-10-01 2013-08-16 アラインメント装置およびアラインメント方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2013169208A Withdrawn JP2014013916A (ja) 2008-10-01 2013-08-16 アラインメント装置およびアラインメント方法

Country Status (3)

Country Link
JP (2) JP5353892B2 (zh)
TW (1) TW201015661A (zh)
WO (1) WO2010038454A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6264831B2 (ja) * 2012-11-06 2018-01-24 株式会社ニコン アライメント装置、位置合わせ方法、及び、積層半導体装置の製造方法
KR101708143B1 (ko) * 2013-06-17 2017-02-17 에베 그룹 에. 탈너 게엠베하 기판 정렬 장치 및 방법
KR101741384B1 (ko) 2013-12-06 2017-05-29 에베 그룹 에. 탈너 게엠베하 기질들을 정렬하기 위한 장치 및 방법
JP5971367B2 (ja) * 2015-03-04 2016-08-17 株式会社ニコン 基板重ね合わせ装置および基板重ね合わせ方法
JP6596330B2 (ja) * 2015-12-25 2019-10-23 東京エレクトロン株式会社 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP6487355B2 (ja) * 2016-03-08 2019-03-20 ボンドテック株式会社 アライメント装置
EP3734650B1 (de) 2016-08-29 2023-09-27 EV Group E. Thallner GmbH Verfahren und vorrichtung zum ausrichten von substraten
JP7152602B2 (ja) * 2019-05-08 2022-10-12 東京エレクトロン株式会社 接合装置、接合システム及び接合方法
US11209373B2 (en) * 2019-06-21 2021-12-28 Kla Corporation Six degree of freedom workpiece stage
KR20220047756A (ko) * 2019-08-23 2022-04-19 에베 그룹 에. 탈너 게엠베하 기판의 정렬을 위한 방법 및 장치
JP7130720B2 (ja) * 2020-11-25 2022-09-05 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板を位置合わせする方法および装置
KR102653108B1 (ko) * 2021-10-28 2024-04-02 코스텍시스템(주) 기판 정렬 장치 및 이를 이용한 기판 정렬 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236165A (ja) * 2004-02-23 2005-09-02 Bondotekku:Kk ピエゾボンディングテーブル
JP2005251972A (ja) * 2004-03-04 2005-09-15 Nikon Corp ウェハ重ね合わせ方法及びウェハ重ね合わせ装置
JP2005302858A (ja) * 2004-04-08 2005-10-27 Nikon Corp ウェハの接合装置
JP2006100656A (ja) * 2004-09-30 2006-04-13 Nikon Corp ウェハ積層時の重ね合わせ方法
JP2007158200A (ja) * 2005-12-08 2007-06-21 Nikon Corp 貼り合わせ半導体装置製造用の露光方法
JP2009231671A (ja) * 2008-03-25 2009-10-08 Nikon Corp アラインメント装置
JP2009245963A (ja) * 2008-03-28 2009-10-22 Nikon Corp アラインメント装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236165A (ja) * 2004-02-23 2005-09-02 Bondotekku:Kk ピエゾボンディングテーブル
JP2005251972A (ja) * 2004-03-04 2005-09-15 Nikon Corp ウェハ重ね合わせ方法及びウェハ重ね合わせ装置
JP2005302858A (ja) * 2004-04-08 2005-10-27 Nikon Corp ウェハの接合装置
JP2006100656A (ja) * 2004-09-30 2006-04-13 Nikon Corp ウェハ積層時の重ね合わせ方法
JP2007158200A (ja) * 2005-12-08 2007-06-21 Nikon Corp 貼り合わせ半導体装置製造用の露光方法
JP2009231671A (ja) * 2008-03-25 2009-10-08 Nikon Corp アラインメント装置
JP2009245963A (ja) * 2008-03-28 2009-10-22 Nikon Corp アラインメント装置

Also Published As

Publication number Publication date
WO2010038454A1 (ja) 2010-04-08
JPWO2010038454A1 (ja) 2012-03-01
TW201015661A (en) 2010-04-16
JP2014013916A (ja) 2014-01-23

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