JP5341781B2 - 電力供給制御回路 - Google Patents
電力供給制御回路 Download PDFInfo
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- JP5341781B2 JP5341781B2 JP2010000133A JP2010000133A JP5341781B2 JP 5341781 B2 JP5341781 B2 JP 5341781B2 JP 2010000133 A JP2010000133 A JP 2010000133A JP 2010000133 A JP2010000133 A JP 2010000133A JP 5341781 B2 JP5341781 B2 JP 5341781B2
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- 238000009792 diffusion process Methods 0.000 claims description 31
- 238000007599 discharging Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 14
- 230000007704 transition Effects 0.000 description 11
- 230000007423 decrease Effects 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Description
図1に、本発明の実施の形態1にかかる電力供給制御回路1の回路図を示す。図1に示す電力供給制御回路1は、ゲート駆動回路31と、出力トランジスタ32と、放電回路33aと、放電回路35と、を備える。また、放電回路33aは、トランジスタ(第1の放電スイッチ)37と、放電遮断回路40aと、容量36と、トランジスタ41と、を有する。放電回路35は、電流制限素子40と、トランジスタ(第2の放電スイッチ)39と、を有する。なお、出力トランジスタ32及びトランジスタ37,41は、NチャネルMOSトランジスタである。トランジスタ39は、デプレッション型のNチャネルMOSトランジスタである。また、放電遮断回路40aとして、ツェナーダイオード40aが用いられている。また、容量36とトランジスタ41とによりブートストラップ回路を構成する。
図3に、本発明の実施の形態2にかかる電力供給制御回路2の回路図を示す。図3に示す電力供給制御回路2は、図1に示す電力供給制御回路1と比較して、放電回路33aの代わりに放電回路33bを備える。放電回路33bは、トランジスタ37と放電遮断回路40bと、容量36と、トランジスタ41と、を有する。放電遮断回路40bは、ゲート−ドレイン間が共通接続されたNチャネルMOSトランジスタ40b1〜40bn(nは自然数)を複数有する。トランジスタ40b1〜40bnは、トランジスタ37のソースと出力トランジスタ32のソースとの間に直列に接続される。その他の回路構成については、図1に示す回路と同様であるため説明を省略する。
図4に、本発明の実施の形態3にかかる電力供給制御回路3の回路図を示す。図4に示す電力供給制御回路3は、図1に示す電力供給制御回路1と比較して、放電回路33aの代わりに放電回路33cを備える。放電回路33cは、トランジスタ37と放電遮断回路40cと、容量36と、トランジスタ41と、を有する。なお、放電遮断回路40cとして、NチャネルMOSトランジスタ40cが用いられている。トランジスタ40cでは、ゲート及びドレインがトランジスタ37のソースに共通接続され、ソースが出力トランジスタ32のソースに接続される。その他の回路構成については、図1に示す回路と同様であるため、説明を省略する。
31 ゲート駆動回路
32 出力トランジスタ
33a,33b,33c 放電回路
35 放電回路
36 容量
37,39,41 トランジスタ
40 電流制限素子
40a,40b,40c 放電遮断回路
40b1〜40bn トランジスタ
Claims (8)
- 電源ラインと出力端子との間に設けられ、前記電源ラインの電圧よりも高い電圧によってゲートが駆動されることで負荷に対して電力を供給するNチャネル型の出力トランジスタと、
外部入力信号に基づいて前記出力トランジスタのオンオフを制御するための制御信号を生成するゲート駆動回路と、
前記出力トランジスタの前記ゲート及びソース間に設けられ、前記出力トランジスタをオフする場合、前記制御信号に基づいて前記出力トランジスタの前記ゲートに蓄積された電荷を放電するための第1の放電スイッチと、
前記出力トランジスタの前記ゲート及びソース間に設けられ、前記出力トランジスタをオフする場合、前記制御信号に基づいて前記出力トランジスタの前記ゲートに蓄積された電荷を前記第1の放電スイッチよりも緩やかに放電するための第2の放電スイッチと、
前記第1の放電スイッチに直列に接続され、前記出力トランジスタをオフする場合において、前記出力トランジスタの前記ゲートの電圧が前記電源ラインの電圧と前記出力トランジスタのしきい値電圧との和よりも大きい所定の電圧レベルに低下した場合、前記出力トランジスタの前記ゲートに蓄積された電荷の放電を遮断する放電遮断回路と、を備えた電力供給制御回路。 - 前記放電遮断回路は、前記出力トランジスタをオフする場合、前記出力端子の電圧が前記電源ラインの電圧よりも低下する前に、前記出力トランジスタの前記ゲートに蓄積された電荷の放電を停止することを特徴とする請求項1に記載の電力供給制御回路。
- 前記放電遮断回路は、ツェナーダイオードであることを特徴とする請求項1又は2に記載の電力供給制御回路。
- 前記放電遮断回路は、ダイオード接続されたNチャネルMOSトランジスタであることを特徴とする請求項1又は2に記載の電力供給制御回路。
- 前記放電遮断回路としてのNチャネルMOSトランジスタでは、ソース領域が前記出力トランジスタのソース領域と同一の拡散層によって形成されていることを特徴とする請求項4に記載の電力供給制御回路。
- 前記放電遮断回路は、ダイオード接続された複数のNチャネルMOSトランジスタが直列に設けられたものであることを特徴とする請求項1又は2に記載の電力供給制御回路。
- 前記第1の放電スイッチはNチャネルMOSトランジスタであって、
前記第1の放電スイッチのゲートに対する電荷の供給を前記制御信号に基づいて制御するブートストラップ回路をさらに備えた請求項1〜6のいずれか一項に記載の電力供給制御回路。 - 前記第2の放電スイッチは、前記制御信号に基づいてオンオフが制御されるデプレッション型のNチャネルMOSトランジスタであることを特徴とする請求項1〜7のいずれか一項に記載の電力供給制御回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2010000133A JP5341781B2 (ja) | 2010-01-04 | 2010-01-04 | 電力供給制御回路 |
US12/979,100 US8373494B2 (en) | 2010-01-04 | 2010-12-27 | Power supply control circuit |
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JP2010000133A JP5341781B2 (ja) | 2010-01-04 | 2010-01-04 | 電力供給制御回路 |
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JP2011139404A JP2011139404A (ja) | 2011-07-14 |
JP5341781B2 true JP5341781B2 (ja) | 2013-11-13 |
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JP2010000133A Active JP5341781B2 (ja) | 2010-01-04 | 2010-01-04 | 電力供給制御回路 |
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JP (1) | JP5341781B2 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5383426B2 (ja) * | 2009-10-23 | 2014-01-08 | ルネサスエレクトロニクス株式会社 | 異常検出時急速放電回路 |
US10574297B2 (en) | 2009-11-25 | 2020-02-25 | Triune Ip, Llc | Multi-use wireless power and data system |
US9231400B2 (en) * | 2011-07-10 | 2016-01-05 | Triune Systems, LLC | Voltage transient protection circuitry |
JP5136544B2 (ja) * | 2009-12-16 | 2013-02-06 | 三菱電機株式会社 | 半導体装置 |
JP5759831B2 (ja) * | 2010-10-25 | 2015-08-05 | ルネサスエレクトロニクス株式会社 | 電力用半導体装置及びその動作方法 |
JP5889723B2 (ja) | 2012-06-07 | 2016-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6919920B2 (ja) * | 2014-10-24 | 2021-08-18 | テキサス インスツルメンツ インコーポレイテッド | 電圧コンバータのためのアダプティブコントローラ |
JP6652561B2 (ja) * | 2014-10-24 | 2020-02-26 | 日本テキサス・インスツルメンツ合同会社 | 電圧コンバータのためのアダプティブコントローラ |
JP6378230B2 (ja) * | 2016-03-15 | 2018-08-22 | 株式会社東芝 | 半導体装置 |
CN106061091B (zh) * | 2016-08-17 | 2018-05-15 | 衢州昀睿工业设计有限公司 | 一种开关电源的控制电路 |
CN112421971A (zh) * | 2019-08-21 | 2021-02-26 | 万国半导体(开曼)股份有限公司 | 一种电源转换系统及控制方法 |
JP7018095B2 (ja) * | 2020-07-07 | 2022-02-09 | 華邦電子股▲ふん▼有限公司 | 電源制御回路 |
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JP3120303B2 (ja) * | 1992-08-10 | 2000-12-25 | 株式会社日立製作所 | パワーmos制御回路 |
JP2002290221A (ja) * | 2001-03-27 | 2002-10-04 | Nec Corp | 半導体出力回路の消費電力低減回路 |
JP4502177B2 (ja) * | 2003-10-14 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 出力回路 |
JP4229804B2 (ja) * | 2003-10-24 | 2009-02-25 | Necエレクトロニクス株式会社 | 半導体出力回路 |
US7834669B2 (en) * | 2007-12-21 | 2010-11-16 | Nec Electronics Corporation | Semiconductor output circuit for controlling power supply to a load |
US7701264B2 (en) * | 2007-12-21 | 2010-04-20 | Nec Electronics Corporation | Semiconductor output circuit |
-
2010
- 2010-01-04 JP JP2010000133A patent/JP5341781B2/ja active Active
- 2010-12-27 US US12/979,100 patent/US8373494B2/en not_active Expired - Fee Related
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US8373494B2 (en) | 2013-02-12 |
JP2011139404A (ja) | 2011-07-14 |
US20110163794A1 (en) | 2011-07-07 |
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