JP5340934B2 - シリコン・オン・インシュレータ構造に使用されるプラズマ浸漬イオン注入処理による表面活性化のための方法 - Google Patents

シリコン・オン・インシュレータ構造に使用されるプラズマ浸漬イオン注入処理による表面活性化のための方法 Download PDF

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Publication number
JP5340934B2
JP5340934B2 JP2009523910A JP2009523910A JP5340934B2 JP 5340934 B2 JP5340934 B2 JP 5340934B2 JP 2009523910 A JP2009523910 A JP 2009523910A JP 2009523910 A JP2009523910 A JP 2009523910A JP 5340934 B2 JP5340934 B2 JP 5340934B2
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Prior art keywords
substrate
silicon oxide
dry cleaning
cleaning process
oxide layer
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Japanese (ja)
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JP2010500761A (ja
JP2010500761A5 (enExample
Inventor
ランディール ピー． エス． タクール，
スティーブン モファッティ，
パー オブ ハンソン，
スティーブ ハナエム，
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32412—Plasma immersion ion implantation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Analytical Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2009523910A 2006-08-09 2007-08-02 シリコン・オン・インシュレータ構造に使用されるプラズマ浸漬イオン注入処理による表面活性化のための方法 Expired - Fee Related JP5340934B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/463,425 US7745309B2 (en) 2006-08-09 2006-08-09 Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure
US11/463,425 2006-08-09
PCT/US2007/075118 WO2008021746A2 (en) 2006-08-09 2007-08-02 Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure

Publications (3)

Publication Number Publication Date
JP2010500761A JP2010500761A (ja) 2010-01-07
JP2010500761A5 JP2010500761A5 (enExample) 2010-09-16
JP5340934B2 true JP5340934B2 (ja) 2013-11-13

Family

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Family Applications (1)

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JP2009523910A Expired - Fee Related JP5340934B2 (ja) 2006-08-09 2007-08-02 シリコン・オン・インシュレータ構造に使用されるプラズマ浸漬イオン注入処理による表面活性化のための方法

Country Status (4)

Country Link
US (1) US7745309B2 (enExample)
JP (1) JP5340934B2 (enExample)
TW (1) TWI366237B (enExample)
WO (1) WO2008021746A2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7390708B2 (en) * 2006-10-23 2008-06-24 Interuniversitair Microelektronica Centrum (Imec) Vzw Patterning of doped poly-silicon gates
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
WO2009152648A1 (zh) * 2008-06-20 2009-12-23 Lee Tienhsi 薄膜制造方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
EP2282332B1 (en) * 2009-08-04 2012-06-27 S.O.I. TEC Silicon Method for fabricating a semiconductor substrate
TWI402898B (zh) * 2009-09-03 2013-07-21 Atomic Energy Council 鈍化修補太陽能電池缺陷之方法
EP3024014B9 (de) 2011-01-25 2019-04-24 EV Group E. Thallner GmbH Verfahren zum permanenten bonden von wafern
CN103477420B (zh) 2011-04-08 2016-11-16 Ev集团E·索尔纳有限责任公司 永久性粘合晶片的方法
US8987096B2 (en) * 2012-02-07 2015-03-24 United Microelectronics Corp. Semiconductor process
WO2014015899A1 (de) * 2012-07-24 2014-01-30 Ev Group E. Thallner Gmbh Verfahren und vorrichtung zum permanenten bonden von wafern
US8951896B2 (en) 2013-06-28 2015-02-10 International Business Machines Corporation High linearity SOI wafer for low-distortion circuit applications
EP3608973A1 (en) * 2018-08-08 2020-02-12 Meyer Burger Research AG Method for manufacturing photovoltaic devices and photovoltaic devices made with the method
CN117174728B (zh) * 2023-11-02 2024-02-20 合肥新晶集成电路有限公司 晶圆处理方法及晶圆结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472522A (en) * 1987-09-14 1989-03-17 Nippon Telegraph & Telephone Apparatus for manufacturing semiconductor substrate
JPH0391227A (ja) * 1989-09-01 1991-04-16 Nippon Soken Inc 半導体基板の接着方法
JP2910334B2 (ja) * 1991-07-22 1999-06-23 富士電機株式会社 接合方法
US6536449B1 (en) * 1997-11-17 2003-03-25 Mattson Technology Inc. Downstream surface cleaning process
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
US6893907B2 (en) 2002-06-05 2005-05-17 Applied Materials, Inc. Fabrication of silicon-on-insulator structure using plasma immersion ion implantation
US7183177B2 (en) 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US7465478B2 (en) 2000-08-11 2008-12-16 Applied Materials, Inc. Plasma immersion ion implantation process
FR2864336B1 (fr) * 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
JP4730645B2 (ja) * 2004-02-13 2011-07-20 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの製造方法
US7261793B2 (en) * 2004-08-13 2007-08-28 Hewlett-Packard Development Company, L.P. System and method for low temperature plasma-enhanced bonding

Also Published As

Publication number Publication date
TWI366237B (en) 2012-06-11
JP2010500761A (ja) 2010-01-07
US20080038900A1 (en) 2008-02-14
TW200822241A (en) 2008-05-16
WO2008021746A2 (en) 2008-02-21
WO2008021746A3 (en) 2008-04-03
US7745309B2 (en) 2010-06-29

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