JP5314889B2 - 電子装置及びその製造方法及び配線基板及びその製造方法 - Google Patents
電子装置及びその製造方法及び配線基板及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/02—Arrangements for de-icing; Arrangements for drying-out ; Arrangements for cooling; Arrangements for preventing corrosion
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- H—ELECTRICITY
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- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
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- H01L2223/66—High-frequency adaptations
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0323—Working metal substrate or core, e.g. by etching, deforming
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Thermal Sciences (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
11 配線基板
12 電子部品
13 多層配線構造体
14,24,36 絶縁層
14A,14B,14C 開口部
16,17,18 第1のビア
20,21,22 第1の配線
27,28,29 第2のビア
32,33,34 第2の配線
39,40,41 第3のビア
42,43,44,45,46 第3の配線
48 保護膜
51 第1の外部接続端子
52,53,54,55 第2の外部接続端子
57 放熱板
58 除去部
60 ダイポールアンテナ
61 アンダーフィル樹脂
70 金属板
Claims (22)
- 積層された絶縁層及び配線層を有し、一方の面とその反対側の他方の面とを有する多層配線構造体と、
前記多層配線構造体の一方の面に搭載された電子部品と、
前記多層配線構造体の他方の面に形成された放熱部材及び前記多層配線構造体の他方の面の端部位置に形成されたアンテナと、
前記多層配線構造体内に形成され、一端が前記放熱部材と熱的に接続され、他端部が前記電子部品と熱的に接続された放熱経路と、
前記多層配線構造体内に形成され、前記アンテナと前記電子部品を接続する配線と、
を有し、
前記放熱部材と、前記アンテナと、は別の部材として形成され、間隔を空けて対向するように配置されており、
前記放熱部材は前記電子部品と対向して配置された電子装置。 - 前記放熱部材と前記アンテナとが、単一の金属板または金属箔から形成されている請求項1記載の電子装置。
- 前記電子部品は、放熱用のサーマルバンプを介して前記放熱経路と熱的に接続されてなる請求項1または2に記載の電子装置。
- 前記放熱部材をグランド接続してなる請求項1乃至3のいずれか一項に記載の電子装置。
- 前記放熱部材と前記配線とで、マイクロストリップ線路が形成されてなる請求項4記載の電子装置。
- 前記アンテナは前記多層配線構造体の他方の面の端部に形成され、
前記放熱部材は、前記多層配線構造体の他方の面の全面積の70〜80%の面積を占めている請求項1乃至5のいずれか一項に記載の電子装置。 - 前記放熱部材の形成領域が、前記アンテナにより分断されていない請求項1乃至6のいずれか一項に記載の電子装置。
- 支持板上に絶縁層と配線層とを積層し、前記支持板に接する他方の面と、その反対側の一方の面とを有する多層配線構造体を形成する工程と、
前記他方の面に、前記支持板から形成した放熱部材及び前記他方の面の端部位置に、前記支持板から形成したアンテナを設ける工程と、
前記一方の面に、電子部品を実装する工程と、を有し、
前記多層配線構造体の形成工程時に、前記多層配線構造体内に、一端が前記放熱部材と熱的に接続され他端が前記電子部品と接続される放熱経路と、前記アンテナと前記電子部品とを接続する配線とが形成され、
前記放熱部材と、前記アンテナと、は別の部材として形成され、間隔を空けて対向するように配置されており、
前記放熱部材は前記電子部品と対向して配置されていることを特徴とする電子装置の製造方法。 - 前記支持板が金属箔または金属板からなり、前記支持板をパターニングして前記放熱部材及び前記アンテナを同時に形成する請求項8記載の電子装置の製造方法。
- 前記電子部品に放熱用のサーマルバンプを設け、
該サーマルバンプを前記放熱経路に熱的に接続させる請求項8または9に記載の電子装置の製造方法。 - 前記アンテナは前記多層配線構造体の他方の面の端部に形成され、
前記放熱部材は、前記多層配線構造体の他方の面の全面積の70〜80%の面積を占めている請求項8乃至10のいずれか一項に記載の電子装置の製造方法。 - 前記放熱部材の形成領域が、前記アンテナにより分断されていない請求項8乃至11のいずれか一項に記載の電子装置の製造方法。
- 電子部品が実装される配線基板であって、
積層された絶縁層及び配線層を有し、一方の面とその反対側の他方の面とを有する多層配線構造体と、
前記多層配線構造体の他方の面に形成された放熱部材及び前記多層配線構造体の他方の面の端部位置に形成されたアンテナと、
前記多層配線構造体内に形成され、一端が前記放熱部材と熱的に接続され、他端部が前記電子部品と熱的に接続される放熱経路と、
前記多層配線構造体内に形成され、前記アンテナと前記電子部品を接続する配線と、
を有し、
前記放熱部材と、前記アンテナと、は別の部材として形成され、間隔を空けて対向するように配置された配線基板。 - 前記放熱部材と前記アンテナとが、単一の金属板または金属箔から形成されている請求項13記載の配線基板。
- 前記電子部品は、放熱用のサーマルバンプを介して前記放熱経路と熱的に接続されてなる請求項13または14に記載の配線基板。
- 前記放熱部材をグランド接続してなる請求項13乃至15のいずれか一項に記載の配線基板。
- 前記放熱部材と前記配線とで、マイクロストリップ線路が形成されてなる請求項16記載の配線基板。
- 前記アンテナは前記多層配線構造体の他方の面の端部に形成され、
前記放熱部材は、前記多層配線構造体の他方の面の全面積の70〜80%の面積を占めている請求項13乃至17のいずれか一項に記載の配線基板。 - 前記放熱部材の形成領域が、前記アンテナにより分断されていない請求項13乃至18のいずれか一項に記載の配線基板。
- 電子部品が実装される配線基板の製造方法であって、
支持板上に絶縁層と配線層とを積層し、前記支持板に接する他方の面と、その反対側の一方の面とを有する多層配線構造体を形成する工程と、
前記他方の面に、前記支持板から形成した放熱部材及び前記他方の面の端部位置に、前記支持板から形成したアンテナを設ける工程と、を有し、
前記多層配線構造体の形成工程時に、前記多層配線構造体内に、一端が前記放熱部材と熱的に接続され他端が前記電子部品と接続される放熱経路と、前記アンテナと前記電子部品とを接続する配線とが形成され、
前記放熱部材と、前記アンテナと、は別の部材として形成され、間隔を空けて対向するように配置されたことを特徴とする配線基板の製造方法。 - 前記アンテナは前記多層配線構造体の他方の面の端部に形成され、
前記放熱部材は、前記多層配線構造体の他方の面の全面積の70〜80%の面積を占めている請求項20に記載の配線基板の製造方法。 - 前記放熱部材の形成領域が、前記アンテナにより分断されていない請求項20または21に記載の配線基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007335691A JP5314889B2 (ja) | 2007-12-27 | 2007-12-27 | 電子装置及びその製造方法及び配線基板及びその製造方法 |
US12/342,823 US8053677B2 (en) | 2007-12-27 | 2008-12-23 | Electronic apparatus and method of manufacturing the same, and wiring substrate and method of manufacturing the same |
KR1020080133189A KR101454419B1 (ko) | 2007-12-27 | 2008-12-24 | 전자 장치 및 그 제조 방법과, 배선 기판 및 그 제조 방법 |
TW097150907A TW200934350A (en) | 2007-12-27 | 2008-12-26 | Electronic apparatus and method of manufacturing the same, and wiring substrate and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007335691A JP5314889B2 (ja) | 2007-12-27 | 2007-12-27 | 電子装置及びその製造方法及び配線基板及びその製造方法 |
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JP2009158744A JP2009158744A (ja) | 2009-07-16 |
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KR100704919B1 (ko) * | 2005-10-14 | 2007-04-09 | 삼성전기주식회사 | 코어층이 없는 기판 및 그 제조 방법 |
US8319318B2 (en) * | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US20110253439A1 (en) * | 2010-04-20 | 2011-10-20 | Subtron Technology Co. Ltd. | Circuit substrate and manufacturing method thereof |
US8411444B2 (en) * | 2010-09-15 | 2013-04-02 | International Business Machines Corporation | Thermal interface material application for integrated circuit cooling |
JP5879030B2 (ja) * | 2010-11-16 | 2016-03-08 | 新光電気工業株式会社 | 電子部品パッケージ及びその製造方法 |
JP5634571B2 (ja) * | 2012-12-21 | 2014-12-03 | キヤノン株式会社 | プリント配線板、プリント回路板及びプリント回路板の製造方法 |
KR101428754B1 (ko) * | 2013-05-14 | 2014-08-11 | (주)실리콘화일 | 방열 특성이 개선된 반도체 장치 |
KR101457338B1 (ko) * | 2013-07-15 | 2014-11-04 | 대덕전자 주식회사 | 회로배선판 제조방법 |
WO2015198770A1 (ja) * | 2014-06-25 | 2015-12-30 | 株式会社村田製作所 | 電子機器 |
US11195787B2 (en) * | 2016-02-17 | 2021-12-07 | Infineon Technologies Ag | Semiconductor device including an antenna |
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JP3472678B2 (ja) * | 1997-02-20 | 2003-12-02 | シャープ株式会社 | アンテナ一体化マイクロ波・ミリ波回路 |
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US20050029666A1 (en) * | 2001-08-31 | 2005-02-10 | Yasutoshi Kurihara | Semiconductor device structural body and electronic device |
JP4912716B2 (ja) * | 2006-03-29 | 2012-04-11 | 新光電気工業株式会社 | 配線基板の製造方法、及び半導体装置の製造方法 |
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