JP5305599B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
JP5305599B2
JP5305599B2 JP2007038288A JP2007038288A JP5305599B2 JP 5305599 B2 JP5305599 B2 JP 5305599B2 JP 2007038288 A JP2007038288 A JP 2007038288A JP 2007038288 A JP2007038288 A JP 2007038288A JP 5305599 B2 JP5305599 B2 JP 5305599B2
Authority
JP
Japan
Prior art keywords
wiring
layer
barrier layer
cual
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007038288A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008205119A (ja
JP2008205119A5 (https=
Inventor
健壹 森
和義 前川
則晶 天羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007038288A priority Critical patent/JP5305599B2/ja
Priority to US12/071,200 priority patent/US20080197496A1/en
Publication of JP2008205119A publication Critical patent/JP2008205119A/ja
Publication of JP2008205119A5 publication Critical patent/JP2008205119A5/ja
Application granted granted Critical
Publication of JP5305599B2 publication Critical patent/JP5305599B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H10W20/4424—Copper alloys
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2007038288A 2007-02-19 2007-02-19 半導体装置およびその製造方法 Expired - Fee Related JP5305599B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007038288A JP5305599B2 (ja) 2007-02-19 2007-02-19 半導体装置およびその製造方法
US12/071,200 US20080197496A1 (en) 2007-02-19 2008-02-19 Semiconductor device having at least two layers of wirings stacked therein and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007038288A JP5305599B2 (ja) 2007-02-19 2007-02-19 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2008205119A JP2008205119A (ja) 2008-09-04
JP2008205119A5 JP2008205119A5 (https=) 2010-04-02
JP5305599B2 true JP5305599B2 (ja) 2013-10-02

Family

ID=39705945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007038288A Expired - Fee Related JP5305599B2 (ja) 2007-02-19 2007-02-19 半導体装置およびその製造方法

Country Status (2)

Country Link
US (1) US20080197496A1 (https=)
JP (1) JP5305599B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404582B2 (en) * 2010-05-04 2013-03-26 International Business Machines Corporation Structure and method for manufacturing interconnect structures having self-aligned dielectric caps
JP2012043977A (ja) 2010-08-19 2012-03-01 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US20140138837A1 (en) * 2012-11-20 2014-05-22 Stmicroelectronics, Inc. Sandwiched diffusion barrier and metal liner for an interconnect structure
US9293412B2 (en) * 2012-12-17 2016-03-22 International Business Machines Corporation Graphene and metal interconnects with reduced contact resistance
KR102624631B1 (ko) * 2016-12-02 2024-01-12 삼성전자주식회사 반도체 장치
KR102634781B1 (ko) 2017-01-18 2024-02-13 삼성전자주식회사 자기 메모리 장치
KR102450580B1 (ko) * 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
JP7343407B2 (ja) * 2020-01-15 2023-09-12 株式会社アルバック 金属配線の形成方法及び金属配線構造体
JP7449790B2 (ja) * 2020-06-24 2024-03-14 株式会社アルバック 金属配線の形成方法及び金属配線の構造体

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346745B1 (en) * 1998-12-04 2002-02-12 Advanced Micro Devices, Inc. Cu-A1 combined interconnect system
JP3643533B2 (ja) * 2000-12-27 2005-04-27 株式会社東芝 半導体装置およびその製造方法
US6737747B2 (en) * 2002-01-15 2004-05-18 International Business Machines Corporation Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof
JP3992588B2 (ja) * 2002-10-23 2007-10-17 東京エレクトロン株式会社 成膜方法
US20040183202A1 (en) * 2003-01-31 2004-09-23 Nec Electronics Corporation Semiconductor device having copper damascene interconnection and fabricating method thereof
JP2004253781A (ja) * 2003-01-31 2004-09-09 Nec Electronics Corp 半導体装置およびその製造方法
JP4454242B2 (ja) * 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2007042662A (ja) * 2003-10-20 2007-02-15 Renesas Technology Corp 半導体装置
US7215006B2 (en) * 2005-10-07 2007-05-08 International Business Machines Corporation Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement

Also Published As

Publication number Publication date
US20080197496A1 (en) 2008-08-21
JP2008205119A (ja) 2008-09-04

Similar Documents

Publication Publication Date Title
JP5305599B2 (ja) 半導体装置およびその製造方法
US9076792B2 (en) Multi-layer barrier layer stacks for interconnect structures
CN101000905B (zh) 半导体装置以及半导体装置的制造方法
JP6415376B2 (ja) 半導体装置およびその製造方法
US6780769B2 (en) Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer
CN101465315A (zh) 集成电路结构及其形成方法
US9269615B2 (en) Multi-layer barrier layer for interconnect structure
TW200426991A (en) Semiconductor device and method of manufacturing the same
US20070054489A1 (en) Interconnect structures with encasing cap and methods of making thereof
JP5089850B2 (ja) 半導体装置
US8004087B2 (en) Semiconductor device with dual damascene wirings and method for manufacturing same
KR100939773B1 (ko) 반도체 소자의 금속배선 및 그의 형성방법
US8728931B2 (en) Multi-layer barrier layer for interconnect structure
US7682967B2 (en) Method of forming metal wire in semiconductor device
US7659626B2 (en) Semiconductor device including a barrier metal film
US20060202336A1 (en) Semiconductor device and method of fabricating a semiconductor device
JP2008159720A (ja) 半導体装置並びに半導体装置の製造方法
JP2009170665A (ja) 半導体装置および半導体装置の製造方法
JP2012039019A (ja) 半導体装置およびその製造方法
KR20080001905A (ko) 반도체 소자의 금속 배선 형성방법
JP2006270080A (ja) 半導体装置及びその製造方法
JP2008147252A (ja) 半導体装置とその製造方法
JP2009111258A (ja) 半導体装置およびその製造方法
KR20100076332A (ko) 반도체 소자의 금속 배선 형성 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100215

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100215

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100526

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121022

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121030

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130319

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130514

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130618

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130625

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5305599

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees