JP5285580B2 - パッケージ構造の製造方法 - Google Patents

パッケージ構造の製造方法 Download PDF

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Publication number
JP5285580B2
JP5285580B2 JP2009263063A JP2009263063A JP5285580B2 JP 5285580 B2 JP5285580 B2 JP 5285580B2 JP 2009263063 A JP2009263063 A JP 2009263063A JP 2009263063 A JP2009263063 A JP 2009263063A JP 5285580 B2 JP5285580 B2 JP 5285580B2
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JP
Japan
Prior art keywords
layer
package substrate
package
bump
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009263063A
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English (en)
Japanese (ja)
Other versions
JP2011054921A5 (https=
JP2011054921A (ja
Inventor
胡竹青
Original Assignee
欣興電子股▲分▼有限公司
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Publication date
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Publication of JP2011054921A publication Critical patent/JP2011054921A/ja
Publication of JP2011054921A5 publication Critical patent/JP2011054921A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2009263063A 2009-09-02 2009-11-18 パッケージ構造の製造方法 Expired - Fee Related JP5285580B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW098129496 2009-09-02
TW098129496A TWI388019B (zh) 2009-09-02 2009-09-02 封裝結構之製法

Publications (3)

Publication Number Publication Date
JP2011054921A JP2011054921A (ja) 2011-03-17
JP2011054921A5 JP2011054921A5 (https=) 2013-01-10
JP5285580B2 true JP5285580B2 (ja) 2013-09-11

Family

ID=43625513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009263063A Expired - Fee Related JP5285580B2 (ja) 2009-09-02 2009-11-18 パッケージ構造の製造方法

Country Status (3)

Country Link
US (1) US8222080B2 (https=)
JP (1) JP5285580B2 (https=)
TW (1) TWI388019B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI425886B (zh) * 2011-06-07 2014-02-01 欣興電子股份有限公司 嵌埋有電子元件之封裝結構及其製法
HK1167067A2 (en) * 2011-09-06 2012-11-16 Centricam Technologies Limited A system and method for processing a very wide angle image
JP2013214578A (ja) * 2012-03-30 2013-10-17 Ibiden Co Ltd 配線板及びその製造方法
JP2014229698A (ja) * 2013-05-21 2014-12-08 イビデン株式会社 配線板及び配線板の製造方法
TWI551207B (zh) * 2014-09-12 2016-09-21 矽品精密工業股份有限公司 基板結構及其製法
TWI570816B (zh) * 2014-09-26 2017-02-11 矽品精密工業股份有限公司 封裝結構及其製法
US10504871B2 (en) 2017-12-11 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10818636B2 (en) 2018-08-30 2020-10-27 Advanced Semiconductor Engineering, Inc. Substrate panel structure and manufacturing process
US10624213B1 (en) * 2018-12-20 2020-04-14 Intel Corporation Asymmetric electronic substrate and method of manufacture
US11545455B2 (en) * 2019-05-28 2023-01-03 Apple Inc. Semiconductor packaging substrate fine pitch metal bump and reinforcement structures
US11694906B2 (en) 2019-09-03 2023-07-04 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11605552B2 (en) 2020-02-21 2023-03-14 Amkor Technology Singapore Holding Pte. Ltd. Hybrid panel method of manufacturing electronic devices and electronic devices manufactured thereby
US11915949B2 (en) 2020-02-21 2024-02-27 Amkor Technology Singapore Holding Pte. Ltd. Hybrid panel method of manufacturing electronic devices and electronic devices manufactured thereby

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111395A (ja) * 1981-12-25 1983-07-02 株式会社日立製作所 混成集積回路の製造方法
JP4115560B2 (ja) * 1997-09-22 2008-07-09 シチズンホールディングス株式会社 半導体パッケージの製造方法
JP5410660B2 (ja) * 2007-07-27 2014-02-05 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置及びその製造方法
TWI328423B (en) * 2007-09-14 2010-08-01 Unimicron Technology Corp Circuit board structure having heat-dissipating structure
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US7790503B2 (en) * 2007-12-18 2010-09-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device module
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법

Also Published As

Publication number Publication date
TW201110247A (en) 2011-03-16
US20110053318A1 (en) 2011-03-03
US8222080B2 (en) 2012-07-17
JP2011054921A (ja) 2011-03-17
TWI388019B (zh) 2013-03-01

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