JP5264640B2 - 積層型半導体装置及びその製造方法 - Google Patents

積層型半導体装置及びその製造方法 Download PDF

Info

Publication number
JP5264640B2
JP5264640B2 JP2009173037A JP2009173037A JP5264640B2 JP 5264640 B2 JP5264640 B2 JP 5264640B2 JP 2009173037 A JP2009173037 A JP 2009173037A JP 2009173037 A JP2009173037 A JP 2009173037A JP 5264640 B2 JP5264640 B2 JP 5264640B2
Authority
JP
Japan
Prior art keywords
jig
opening
common electrode
semiconductor device
chip structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009173037A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011029370A (ja
JP2011029370A5 (enExample
Inventor
昌宏 春原
昭仁 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009173037A priority Critical patent/JP5264640B2/ja
Publication of JP2011029370A publication Critical patent/JP2011029370A/ja
Publication of JP2011029370A5 publication Critical patent/JP2011029370A5/ja
Application granted granted Critical
Publication of JP5264640B2 publication Critical patent/JP5264640B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009173037A 2009-07-24 2009-07-24 積層型半導体装置及びその製造方法 Active JP5264640B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009173037A JP5264640B2 (ja) 2009-07-24 2009-07-24 積層型半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009173037A JP5264640B2 (ja) 2009-07-24 2009-07-24 積層型半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2011029370A JP2011029370A (ja) 2011-02-10
JP2011029370A5 JP2011029370A5 (enExample) 2012-07-12
JP5264640B2 true JP5264640B2 (ja) 2013-08-14

Family

ID=43637784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009173037A Active JP5264640B2 (ja) 2009-07-24 2009-07-24 積層型半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP5264640B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6727111B2 (ja) * 2016-12-20 2020-07-22 新光電気工業株式会社 半導体装置及びその製造方法
CN111081687B (zh) * 2019-12-16 2022-02-01 东莞记忆存储科技有限公司 一种堆叠式芯片封装结构及其封装方法
WO2021199447A1 (ja) * 2020-04-03 2021-10-07 ウルトラメモリ株式会社 メモリユニット、半導体モジュール、dimmモジュール、及びそれらの製造方法
CN114582842B (zh) * 2022-02-28 2025-11-07 珠海天成先进半导体科技有限公司 一种形成三维立体堆叠芯片结构的底部填充方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2670323B1 (fr) * 1990-12-11 1997-12-12 Thomson Csf Procede et dispositif d'interconnexion de circuits integres en trois dimensions.
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
KR100379835B1 (ko) * 1998-12-31 2003-06-19 앰코 테크놀로지 코리아 주식회사 반도체패키지및그제조방법
JP3476383B2 (ja) * 1999-05-27 2003-12-10 シャープ株式会社 半導体積層パッケージ
JP2009071095A (ja) * 2007-09-14 2009-04-02 Spansion Llc 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2011029370A (ja) 2011-02-10

Similar Documents

Publication Publication Date Title
US8835228B2 (en) Substrate-less stackable package with wire-bond interconnect
US8659151B2 (en) Semiconductor device and manufacturing method thereof
KR101734882B1 (ko) 영역 어레이 유닛 컨넥터를 갖는 적층 가능한 몰딩된 마이크로전자 패키지
US10229892B2 (en) Semiconductor package and method for manufacturing a semiconductor package
US9029199B2 (en) Method for manufacturing semiconductor device
JP4651359B2 (ja) 半導体装置およびその製造方法
JP5942823B2 (ja) 電子部品装置の製造方法、電子部品装置及び電子装置
KR20100087329A (ko) 칩 스케일 적층형 다이 패키지
KR20040092435A (ko) 반도체 장치 및 그 제조 방법
JP2009026805A (ja) 半導体装置及びその製造方法
KR101538541B1 (ko) 반도체 디바이스
JP6770853B2 (ja) リードフレーム及び電子部品装置とそれらの製造方法
JP2010263080A (ja) 半導体装置
CN101252092B (zh) 多芯片封装结构及其制作方法
JP5264640B2 (ja) 積層型半導体装置及びその製造方法
JP4334397B2 (ja) 半導体装置及びその製造方法
JP2006100666A (ja) 半導体装置及びその製造方法
JP4577316B2 (ja) 半導体装置の製造方法
JP2013110188A (ja) 半導体装置及びその製造方法
JP4979661B2 (ja) 半導体装置の製造方法
TW200935572A (en) Semiconductor chip packaging body and its packaging method
JP4168494B2 (ja) 半導体装置の製造方法
JP2016046509A (ja) プリント配線板および半導体パッケージ
JP4751585B2 (ja) 半導体装置の製造方法
JP2014146741A (ja) 半導体装置の製造方法及び導電性構造体

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120523

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120523

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130405

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130423

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130430

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5264640

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150