JP2011029370A5 - - Google Patents
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- Publication number
- JP2011029370A5 JP2011029370A5 JP2009173037A JP2009173037A JP2011029370A5 JP 2011029370 A5 JP2011029370 A5 JP 2011029370A5 JP 2009173037 A JP2009173037 A JP 2009173037A JP 2009173037 A JP2009173037 A JP 2009173037A JP 2011029370 A5 JP2011029370 A5 JP 2011029370A5
- Authority
- JP
- Japan
- Prior art keywords
- jig
- opening
- chip structure
- common electrode
- wire terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000007747 plating Methods 0.000 claims 7
- 238000004519 manufacturing process Methods 0.000 claims 5
- 239000002184 metal Substances 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- 239000011347 resin Substances 0.000 claims 3
- 229920005989 resin Polymers 0.000 claims 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 238000009713 electroplating Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009173037A JP5264640B2 (ja) | 2009-07-24 | 2009-07-24 | 積層型半導体装置及びその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009173037A JP5264640B2 (ja) | 2009-07-24 | 2009-07-24 | 積層型半導体装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011029370A JP2011029370A (ja) | 2011-02-10 |
| JP2011029370A5 true JP2011029370A5 (enExample) | 2012-07-12 |
| JP5264640B2 JP5264640B2 (ja) | 2013-08-14 |
Family
ID=43637784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009173037A Active JP5264640B2 (ja) | 2009-07-24 | 2009-07-24 | 積層型半導体装置及びその製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5264640B2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6727111B2 (ja) * | 2016-12-20 | 2020-07-22 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| CN111081687B (zh) * | 2019-12-16 | 2022-02-01 | 东莞记忆存储科技有限公司 | 一种堆叠式芯片封装结构及其封装方法 |
| WO2021199447A1 (ja) * | 2020-04-03 | 2021-10-07 | ウルトラメモリ株式会社 | メモリユニット、半導体モジュール、ｄｉｍｍモジュール、及びそれらの製造方法 |
| CN114582842B (zh) * | 2022-02-28 | 2025-11-07 | 珠海天成先进半导体科技有限公司 | 一种形成三维立体堆叠芯片结构的底部填充方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2670323B1 (fr) * | 1990-12-11 | 1997-12-12 | Thomson Csf | Procede et dispositif d'interconnexion de circuits integres en trois dimensions. |
| US5466634A (en) * | 1994-12-20 | 1995-11-14 | International Business Machines Corporation | Electronic modules with interconnected surface metallization layers and fabrication methods therefore |
| KR100379835B1 (ko) * | 1998-12-31 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지및그제조방법 |
| JP3476383B2 (ja) * | 1999-05-27 | 2003-12-10 | シャープ株式会社 | 半導体積層パッケージ |
| JP2009071095A (ja) * | 2007-09-14 | 2009-04-02 | Spansion Llc | 半導体装置の製造方法 |
-
2009
- 2009-07-24 JP JP2009173037A patent/JP5264640B2/ja active Active
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