JP5264401B2 - Pll回路 - Google Patents

Pll回路 Download PDF

Info

Publication number
JP5264401B2
JP5264401B2 JP2008264635A JP2008264635A JP5264401B2 JP 5264401 B2 JP5264401 B2 JP 5264401B2 JP 2008264635 A JP2008264635 A JP 2008264635A JP 2008264635 A JP2008264635 A JP 2008264635A JP 5264401 B2 JP5264401 B2 JP 5264401B2
Authority
JP
Japan
Prior art keywords
frequency
unit
signal
input
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008264635A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010093762A5 (enExample
JP2010093762A (ja
Inventor
善一 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2008264635A priority Critical patent/JP5264401B2/ja
Priority to US12/560,395 priority patent/US8085098B2/en
Publication of JP2010093762A publication Critical patent/JP2010093762A/ja
Publication of JP2010093762A5 publication Critical patent/JP2010093762A5/ja
Application granted granted Critical
Publication of JP5264401B2 publication Critical patent/JP5264401B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2008264635A 2008-10-10 2008-10-10 Pll回路 Expired - Fee Related JP5264401B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008264635A JP5264401B2 (ja) 2008-10-10 2008-10-10 Pll回路
US12/560,395 US8085098B2 (en) 2008-10-10 2009-09-15 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008264635A JP5264401B2 (ja) 2008-10-10 2008-10-10 Pll回路

Publications (3)

Publication Number Publication Date
JP2010093762A JP2010093762A (ja) 2010-04-22
JP2010093762A5 JP2010093762A5 (enExample) 2011-11-10
JP5264401B2 true JP5264401B2 (ja) 2013-08-14

Family

ID=42256002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008264635A Expired - Fee Related JP5264401B2 (ja) 2008-10-10 2008-10-10 Pll回路

Country Status (1)

Country Link
JP (1) JP5264401B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115051648A (zh) * 2022-07-05 2022-09-13 成都天奥电子股份有限公司 一种晶体振荡器自动温度补偿电压获取装置及方法
EP4672603A1 (en) * 2024-06-28 2025-12-31 The Swatch Group Research and Development Ltd ELECTRONIC CIRCUIT AND METHOD FOR ADJUSTING THE TRANSITION TIME OF BUFFER CHAINS IN A BUFFER CHAIN

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132214A (ja) * 1983-01-19 1984-07-30 Toshiba Corp 利得可変回路
US5999028A (en) * 1997-12-22 1999-12-07 Hewlett-Packard Company Differential circuits with adjustable propagation timing
JP3425426B2 (ja) * 2000-01-31 2003-07-14 松下電器産業株式会社 トランスコンダクタおよびフィルタ回路
JP4273729B2 (ja) * 2002-09-18 2009-06-03 ソニー株式会社 可変利得増幅器
JP4866707B2 (ja) * 2006-11-10 2012-02-01 パナソニック株式会社 Pll回路及び信号送受信システム

Also Published As

Publication number Publication date
JP2010093762A (ja) 2010-04-22

Similar Documents

Publication Publication Date Title
US8085098B2 (en) PLL circuit
JP6648218B2 (ja) 位相ロックループ(pll)アーキテクチャ
JP7861895B2 (ja) デジタル-時間変換器
US10193561B2 (en) Phase locked loops
JP5682281B2 (ja) Pll回路
JP4593669B2 (ja) バラツキ補正方法、pll回路及び半導体集積回路
US20200366298A1 (en) Time-to-digital converter and phase locked loop
CN102075181B (zh) 频率合成器及锁频环
US20080100388A1 (en) Frequency-locking device and frequency-locking method thereof
JP4625849B2 (ja) 発振器制御装置
TWI638526B (zh) 頻率合成裝置及其方法
US7741889B2 (en) Phase locked loop with phase rotation for spreading spectrum
CN116015287B (zh) 一种基于频率转电压电路校正tdc步进的方法及装置
JP5231931B2 (ja) Pll回路
JP2010093762A (ja) Pll回路
JP2007184778A (ja) リーク電流補償回路を備えたpll回路
KR100918860B1 (ko) 루프필터 보상회로를 구비하는 주파수 합성기
US20090231003A1 (en) Voltage controlled oscillator and pll and filter using the same
JP4534140B2 (ja) Pll回路
JP4647199B2 (ja) Pll回路
JP2005049233A (ja) ジッタ測定方法、ジッタ測定回路及びこれを備えた発振回路
WO2004013968A1 (ja) デジタルvco及びそのデジタルvcoを用いたpll回路
JP2010056758A (ja) Dll回路
TWI502897B (zh) 壓控振盪器及鎖相迴路
JP5730666B2 (ja) Pll回路

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110922

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110922

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130121

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130312

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130405

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130430

LAPS Cancellation because of no payment of annual fees