JP5254795B2 - デジタル信号にタイムスタンプを付与するためのストローブ技法 - Google Patents

デジタル信号にタイムスタンプを付与するためのストローブ技法 Download PDF

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Publication number
JP5254795B2
JP5254795B2 JP2008532445A JP2008532445A JP5254795B2 JP 5254795 B2 JP5254795 B2 JP 5254795B2 JP 2008532445 A JP2008532445 A JP 2008532445A JP 2008532445 A JP2008532445 A JP 2008532445A JP 5254795 B2 JP5254795 B2 JP 5254795B2
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Japan
Prior art keywords
clock
time stamp
signal
strobe
circuit
Prior art date
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Application number
JP2008532445A
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English (en)
Japanese (ja)
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JP2009510403A (ja
Inventor
サーチェフ，ロナルド・エイ
ウォーカー，アーネスト・ピー
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Teradyne Inc
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Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/234,814 external-priority patent/US7574632B2/en
Priority claimed from US11/234,542 external-priority patent/US7856578B2/en
Priority claimed from US11/234,599 external-priority patent/US7573957B2/en
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of JP2009510403A publication Critical patent/JP2009510403A/ja
Application granted granted Critical
Publication of JP5254795B2 publication Critical patent/JP5254795B2/ja
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Manipulation Of Pulses (AREA)
JP2008532445A 2005-09-23 2006-09-22 デジタル信号にタイムスタンプを付与するためのストローブ技法 Active JP5254795B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US11/234,814 2005-09-23
US11/234,599 2005-09-23
US11/234,814 US7574632B2 (en) 2005-09-23 2005-09-23 Strobe technique for time stamping a digital signal
US11/234,542 2005-09-23
US11/234,542 US7856578B2 (en) 2005-09-23 2005-09-23 Strobe technique for test of digital signal timing
US11/234,599 US7573957B2 (en) 2005-09-23 2005-09-23 Strobe technique for recovering a clock in a digital signal
PCT/US2006/037100 WO2007038340A2 (en) 2005-09-23 2006-09-22 Strobe technique for time stamping a digital signal

Publications (2)

Publication Number Publication Date
JP2009510403A JP2009510403A (ja) 2009-03-12
JP5254795B2 true JP5254795B2 (ja) 2013-08-07

Family

ID=37900290

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2008532445A Active JP5254795B2 (ja) 2005-09-23 2006-09-22 デジタル信号にタイムスタンプを付与するためのストローブ技法
JP2008532401A Active JP5254794B2 (ja) 2005-09-23 2006-09-22 デジタル信号のタイミングを試験するためのストローブ技法
JP2008532444A Active JP4907663B2 (ja) 2005-09-23 2006-09-22 デジタル信号においてクロックを再生するストローブ技法

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2008532401A Active JP5254794B2 (ja) 2005-09-23 2006-09-22 デジタル信号のタイミングを試験するためのストローブ技法
JP2008532444A Active JP4907663B2 (ja) 2005-09-23 2006-09-22 デジタル信号においてクロックを再生するストローブ技法

Country Status (4)

Country Link
EP (3) EP1927210A2 (ko)
JP (3) JP5254795B2 (ko)
KR (3) KR101237878B1 (ko)
WO (3) WO2007038340A2 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7856578B2 (en) 2005-09-23 2010-12-21 Teradyne, Inc. Strobe technique for test of digital signal timing
US7573957B2 (en) 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for recovering a clock in a digital signal
US7574632B2 (en) 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for time stamping a digital signal
CN102356594B (zh) * 2009-04-30 2015-03-25 爱德万测试株式会社 时钟生成装置、测试装置及时钟生成方法
KR101227670B1 (ko) * 2009-05-11 2013-01-29 가부시키가이샤 어드밴티스트 수신 장치, 시험 장치, 수신 방법 및 시험 방법
JPWO2011033589A1 (ja) * 2009-09-18 2013-02-07 株式会社アドバンテスト 試験装置および試験方法
JPWO2011033588A1 (ja) * 2009-09-18 2013-02-07 株式会社アドバンテスト 試験装置および試験方法
US9906355B2 (en) * 2013-01-09 2018-02-27 Nxp Usa, Inc. On-die signal measurement circuit and method
US9279857B2 (en) 2013-11-19 2016-03-08 Teradyne, Inc. Automated test system with edge steering
KR101738005B1 (ko) 2016-06-10 2017-05-19 (주)제이케이아이 논리 분석기
US10733345B1 (en) * 2018-08-23 2020-08-04 Cadence Design Systems, Inc. Method and system for generating a validation test

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997740A (en) * 1975-05-30 1976-12-14 Bell Telephone Laboratories, Incorporated Pulse train analyzer
US4989202A (en) * 1988-10-14 1991-01-29 Harris Corporation ISDN testing device and method
US5084669A (en) * 1990-03-08 1992-01-28 Telefonaktiebolaget L M Ericsson Direct phase digitization
US5499190A (en) * 1992-01-16 1996-03-12 Hamamatsu Photonics K.K. System for measuring timing relationship between two signals
JP2682334B2 (ja) * 1992-05-29 1997-11-26 日本電気株式会社 画像信号の符号化伝送方法
US5446650A (en) * 1993-10-12 1995-08-29 Tektronix, Inc. Logic signal extraction
US5526286A (en) * 1994-02-16 1996-06-11 Tektronix, Inc. Oversampled logic analyzer
US6173207B1 (en) * 1997-09-22 2001-01-09 Agilent Technologies, Inc. Real-time control system with non-deterministic communication
US6285722B1 (en) * 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery
US6204710B1 (en) * 1998-06-22 2001-03-20 Xilinx, Inc. Precision trim circuit for delay lines
US6198700B1 (en) * 1999-06-04 2001-03-06 Level One Communications, Inc. Method and apparatus for retiming test signals
JP4495308B2 (ja) * 2000-06-14 2010-07-07 株式会社アドバンテスト 半導体デバイス試験方法・半導体デバイス試験装置
JP2002196053A (ja) * 2000-12-25 2002-07-10 Ando Electric Co Ltd Ｉｃ測定装置
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system

Also Published As

Publication number Publication date
JP5254794B2 (ja) 2013-08-07
EP1927204A2 (en) 2008-06-04
JP2009510842A (ja) 2009-03-12
KR20080048487A (ko) 2008-06-02
KR20080047403A (ko) 2008-05-28
KR20080045714A (ko) 2008-05-23
JP4907663B2 (ja) 2012-04-04
KR101239743B1 (ko) 2013-03-06
WO2007038339A3 (en) 2007-12-06
WO2007038339A2 (en) 2007-04-05
WO2007038233A2 (en) 2007-04-05
KR101237878B1 (ko) 2013-02-27
KR101236769B1 (ko) 2013-02-25
EP1927203A2 (en) 2008-06-04
WO2007038340A2 (en) 2007-04-05
WO2007038233A3 (en) 2008-10-30
EP1927210A2 (en) 2008-06-04
JP2009510403A (ja) 2009-03-12
JP2009509174A (ja) 2009-03-05
WO2007038340A3 (en) 2007-11-22

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