JP5191214B2 - コンパレータ回路 - Google Patents
コンパレータ回路 Download PDFInfo
- Publication number
- JP5191214B2 JP5191214B2 JP2007291686A JP2007291686A JP5191214B2 JP 5191214 B2 JP5191214 B2 JP 5191214B2 JP 2007291686 A JP2007291686 A JP 2007291686A JP 2007291686 A JP2007291686 A JP 2007291686A JP 5191214 B2 JP5191214 B2 JP 5191214B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplifier
- comparator circuit
- input
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000003990 capacitor Substances 0.000 claims description 19
- 230000003321 amplification Effects 0.000 claims description 17
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 17
- 238000005070 sampling Methods 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 12
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
- H03F3/45977—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
、入力容量10の電荷をQ1とすると、XN1は、
XN1=a(0−XN1+VOFF)・・・(1)
によって表され、
XN1=[a/(1+a)]VOFF・・・(2)
になる。また、Q1は、
Q1=C(XN1−Vin)=C[[a/(1+a)]VOFF−Vin]・・・(3)
になる。
Q2=C(XN2−0)=CXN2・・・(4)
になる。電荷保存則からQ1とQ2とは等しいので、XN2は、
Q2=CXN2=Q1=C[[a/(1+a)]VOFF−Vin]・・・(5)
XN2=[a/(1+a)]VOFF−Vin・・・(6)
になる。また、Vo2は、
Vo2=a(0−XN2+VOFF)・・・(7)
によって表される。式(6)を式(7)に代入すると、Vo2は、
Vo2=aVin+[a/(1+a)]VOFF・・・(8)
になる。
しかしながら、クロック信号Φ1及びΦ2の周波数を早くして、第一アンプ11を高速で動作するようにした場合は、第一アンプ11の動作が追従しないので、アンプゲインaは低くなってしまう。アンプゲインaが低くなると、式(8)に示したように、オフセット電圧VOFFが十分キャンセルされなくなってしまうと言う課題がある。
さらに、第2の増幅回路の増幅率より増幅回路の増幅率を低くし、コンパレータ回路が入力電圧をコンパレートするときに、第2の増幅回路の帰還と切り離すことによって、高速にコンパレート動作することが可能な構成とした。
スイッチ24は、コンパレータ回路の入力端子VINと入力容量20の一方の端子の間に接続されている。スイッチ25は、接地と入力容量20の一方の端子の間に接続されている。入力容量20の他方の端子は、第一アンプ21の反転入力端子に接続されている。第一アンプ21の非反転入力端子は、接地されている。第一アンプ21の出力端子は、ラッチ回路23を介してコンパレータ回路の出力端子OUTに接続されている。さらに、第一アンプ21の出力端子は、第二アンプ22の入力端子に接続されている。第二アンプ22の出力端子は、スイッチ26を介して第一アンプ21の反転入力端子に接続されている。
XN1=aA(0−XN1+VOFF)・・・(9)
によって表され、
XN1=[aA/(1+aA)]VOFF・・・(10)
になる。また、Q1は、
Q1=C(XN1−Vin)=C[[aA/(1+aA)]VOFF−Vin]・・・(11)
になる。
Q2=C(XN2−0)=CXN2・・・(12)
になる。電荷保存則からQ1とQ2とは等しいので、XN2は、
Q2=CXN2=Q1=C[[a/(1+a)]VOFF−Vin]・・・(13)
XN2=[aA/(1+aA)]VOFF−Vin・・・(14)
になる。また、Vo2は、
Vo2=a(0−XN2+VOFF)・・・(15)
によって表される。式(14)を式(15)に代入すると、Vo2は、
Vo2=aVin+[a/(1+aA)]VOFF・・・(16)
になる。
a/(1+aA)≒0・・・(17)
が成立し、
Vo2≒aVin・・・(18)
が成立する。
21 第一アンプ
22 第二アンプ
23 ラッチ回路
24、25、26 スイッチ
Claims (3)
- 入力容量に入力電圧をサンプルホールドすることによって増幅回路のオフセットをキャンセルするコンパレータ回路において、
前記増幅回路の出力を増幅して前記増幅回路の入力に帰還する第2の増幅回路を設け、前記コンパレータ回路が前記入力電圧をサンプルするときに、前記第2の増幅回路が前記増幅回路に帰還して前記コンパレータ回路の増幅率を高くすることによって、オフセットをキャンセルし、
前記第2の増幅回路の増幅率より前記増幅回路の増幅率を低くすることによって、高速にコンパレート動作することが可能なコンパレータ回路。 - コンパレータ回路入力端子と、
一端が、第1のスイッチを介して前記コンパレータ回路入力端子と、第2のスイッチを介して接地と、接続された入力容量と、
第一入力端子が前記入力容量の他端に接続され、第二入力端子が比較電位と接続された、増幅回路と、
入力端子が前記増幅回路の出力端子に接続され、出力端子が第3のスイッチを介して前記増幅回路の第一入力端子に接続された第2の増幅回路と、
入力端子が前記増幅回路の出力端子に接続され、出力端子がコンパレータ回路出力端子に接続されたラッチ回路と、を備え、
前記第2の増幅回路の増幅率より前記増幅回路の増幅率を低くすることによって、高速にコンパレート動作することが可能なコンパレータ回路。 - サンプルホールド動作中に前記第3のスイッチが接続状態になり、コンパレート動作中に前記第3のスイッチが切断状態になる請求項2に記載のコンパレータ回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007291686A JP5191214B2 (ja) | 2006-12-21 | 2007-11-09 | コンパレータ回路 |
US11/960,284 US7755399B2 (en) | 2006-12-21 | 2007-12-19 | High speed comparator circuit with offset cancellation |
CN2007101691793A CN101252351B (zh) | 2006-12-21 | 2007-12-21 | 比较器电路 |
KR1020070134974A KR101232489B1 (ko) | 2006-12-21 | 2007-12-21 | 콤퍼레이터 회로 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006344413 | 2006-12-21 | ||
JP2006344413 | 2006-12-21 | ||
JP2007291686A JP5191214B2 (ja) | 2006-12-21 | 2007-11-09 | コンパレータ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008178079A JP2008178079A (ja) | 2008-07-31 |
JP5191214B2 true JP5191214B2 (ja) | 2013-05-08 |
Family
ID=39704724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007291686A Active JP5191214B2 (ja) | 2006-12-21 | 2007-11-09 | コンパレータ回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7755399B2 (ja) |
JP (1) | JP5191214B2 (ja) |
KR (1) | KR101232489B1 (ja) |
CN (1) | CN101252351B (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8305131B2 (en) | 2006-03-21 | 2012-11-06 | Maxim Integrated, Inc. | Passive offset and overshoot cancellation for sampled-data circuits |
ATE540408T1 (de) * | 2006-03-21 | 2012-01-15 | Cambridge Analog Technologies Inc | Offsetunterdrückung für probendatenschaltungen |
KR20120058057A (ko) * | 2010-11-29 | 2012-06-07 | 삼성전자주식회사 | 오프셋 제거 회로, 샘플링 회로 및 이미지 센서 |
CN102778910A (zh) * | 2011-05-08 | 2012-11-14 | 曹先国 | 高电压基准 |
CN102647189B (zh) * | 2012-05-22 | 2014-12-10 | 成都启臣微电子有限公司 | 动态比较器 |
JP5982510B2 (ja) | 2015-02-09 | 2016-08-31 | 力晶科技股▲ふん▼有限公司 | 電圧発生回路、レギュレータ回路、半導体記憶装置及び半導体装置 |
KR20170131481A (ko) * | 2015-04-14 | 2017-11-29 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | 공통의 증폭기를 이용하여 adc 및 pga를 구현하는 방법 및 장치 |
JP6608645B2 (ja) * | 2015-08-11 | 2019-11-20 | 学校法人大阪産業大学 | 積分回路、電圧比較回路および電圧時間変換回路 |
TWI577153B (zh) * | 2015-10-08 | 2017-04-01 | 九暘電子股份有限公司 | 乙太網路供電設備的增益電路 |
CN105743507B (zh) * | 2016-02-02 | 2018-09-18 | 东南大学 | 一种应用于流水线型adc的低功耗比较器 |
US10083668B2 (en) * | 2016-03-09 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and electronic device |
US10320297B2 (en) * | 2017-10-25 | 2019-06-11 | Infineon Technologies Ag | Body-diode conduction detector for adaptive controlling of the power stage of power converters |
JP7153479B2 (ja) * | 2018-06-19 | 2022-10-14 | ラピスセミコンダクタ株式会社 | コンパレータ回路 |
JP2021186455A (ja) * | 2020-06-03 | 2021-12-13 | パナソニック株式会社 | 脈拍検出装置及び脈拍検出方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4302689A (en) * | 1979-08-02 | 1981-11-24 | John Fluke Mfg. Co., Inc. | Sample and hold circuit |
US4578646A (en) * | 1984-02-08 | 1986-03-25 | Hitachi, Ltd | Integral-type small signal input circuit |
NL8501492A (nl) * | 1985-05-24 | 1986-12-16 | Philips Nv | Bemonster- en houd-schakelinrichting. |
GB2195068B (en) * | 1986-09-10 | 1991-01-23 | Motorola Inc | Switched capacitor filters |
US4894620A (en) * | 1988-04-11 | 1990-01-16 | At&T Bell Laboratories | Switched-capacitor circuit with large time constant |
JP2762542B2 (ja) * | 1989-04-05 | 1998-06-04 | 日本電気株式会社 | コンパレータ回路 |
JPH03146878A (ja) * | 1989-11-01 | 1991-06-21 | Hitachi Ltd | コンパレータ |
US5331222A (en) * | 1993-04-29 | 1994-07-19 | University Of Maryland | Cochlear filter bank with switched-capacitor circuits |
JPH0792204A (ja) | 1993-09-27 | 1995-04-07 | Toshiba Corp | コンパレータ回路 |
JP3673058B2 (ja) * | 1997-04-08 | 2005-07-20 | 株式会社東芝 | コンパレータ回路 |
US6037809A (en) * | 1998-06-02 | 2000-03-14 | General Electric Company | Apparatus and method for a high frequency clocked comparator and apparatus for multi-phase programmable clock generator |
JP2000183703A (ja) * | 1998-12-10 | 2000-06-30 | Nec Corp | コンパレータ |
JP3737346B2 (ja) * | 2000-08-28 | 2006-01-18 | シャープ株式会社 | サンプルホールド増幅回路とそれを用いたパイプライン型ad変換器およびパイプライン型da変換器 |
-
2007
- 2007-11-09 JP JP2007291686A patent/JP5191214B2/ja active Active
- 2007-12-19 US US11/960,284 patent/US7755399B2/en not_active Expired - Fee Related
- 2007-12-21 CN CN2007101691793A patent/CN101252351B/zh active Active
- 2007-12-21 KR KR1020070134974A patent/KR101232489B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2008178079A (ja) | 2008-07-31 |
US7755399B2 (en) | 2010-07-13 |
CN101252351B (zh) | 2012-07-04 |
US20080197887A1 (en) | 2008-08-21 |
CN101252351A (zh) | 2008-08-27 |
KR20080058267A (ko) | 2008-06-25 |
KR101232489B1 (ko) | 2013-02-12 |
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